Aaron J Brennan

US Patent:

7123113, Oct 17, 2006

Filed:

Jun 11, 2004

Appl. No.:

10/866510

Inventors:

Aaron Brennan - Moscow ID, US
Jonathon Stiff - Beaverton OR, US
Mike McMenamy - Tensed ID, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03B 5/36
H03B 1/00
H03L 1/00
H03L 5/00

US Classification:

331158, 331 74, 331116 FE, 331183, 331186

Abstract:

An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.

US Patent:

7196586, Mar 27, 2007

Filed:

Dec 10, 2004

Appl. No.:

11/009816

Inventors:

Jonathon Stiff - Beaverton OR, US
Aaron Brennan - Moscow ID, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03F 3/04

US Classification:

330311, 330298

Abstract:

An amplifier circuit operable to provide symmetric current limiting. The amplifier circuit includes a common source amplifier for sourcing a current and receiving an voltage input, a current source, and a current limiting device coupled between the common source amplifier and the current source. The current limiting device is operable to limit the current sourced by the common source amplifier. A bias network coupled to the current limiting device biases the current limiting device. An output is coupled to the current limiting device. The amount of current that is sourced to the output of the amplifier circuit may be limited, such that current limiting is symmetrical.

US Patent:

7221233, May 22, 2007

Filed:

Sep 24, 2004

Appl. No.:

10/949176

Inventors:

Aaron Brennan - Moscow ID, US
Mark Lugar - Moscow ID, US
Mike McMenamy - Tensed ID, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03B 5/32

US Classification:

331158, 331116 R

Abstract:

According to embodiments of the invention, a nonvolatile memory such as a flash memory is used to configure a single die after packaging of the die has occurred. Thus, numerous applications may be supported by a single die or optimization within a given application may occur. According to embodiments of the invention, the nonvolatile memory may be accessed through a programming interface, and preferably, through a two-pin programming interface, to normalize parameters such as package parasitics, crystal variations, output dividers, output duty cycle, output edge rates, I/O configuration, and oscillator gain. According to an embodiment of the invention, an XO circuit configuration includes a nonvolatile memory and a stand-alone XO, where the XO circuit configuration does not require a PLL to synthesize a reference frequency produced by the XO.

US Patent:

7332976, Feb 19, 2008

Filed:

Feb 3, 2006

Appl. No.:

11/347189

Inventors:

Aaron Brennan - Moscow ID, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03B 5/36

US Classification:

331 45, 333172

Abstract:

A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

US Patent:

7859355, Dec 28, 2010

Filed:

Mar 22, 2006

Appl. No.:

11/277185

Inventors:

Aaron Brennan - Moscow ID, US
Mike McMenamy - Tensed ID, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03L 5/02

US Classification:

331183, 331 36 C, 331177 V, 331186

Abstract:

An oscillator circuit and system are provided having a peak detector that can determine a peak voltage value from the oscillator. The peak voltage value can then be compared against a predetermined voltage value by a controller coupled to the peak detector. The comparison value is then used to change a bias signal if the peak voltage value is dissimilar from the predetermined voltage value. A variable capacitor or varactor can be formed from a transistor and is coupled to the oscillator for receiving the bias signal upon a varactor bias node. The bias signal is used to regulate the capacitance within the varactor as applied to the oscillator nodes. Another controller can also be coupled to the peak detector to produce a second bias signal if the peak voltage is dissimilar from a second predetermined voltage value. The second bias signal can then be forwarded into an amplifier having a variable gain to regulate the gain applied to the oscillator. The combination of a varactor and variable gain amplifier regulate the negative resistance applied to the resonating circuit during startup and steady state operations to ensure a relatively fast startup, and to maintain optimal loading and accurate steady state amplitude after startup has completed.

US Patent:

7902933, Mar 8, 2011

Filed:

Mar 28, 2007

Appl. No.:

11/692887

Inventors:

Aaron Brennan - Moscow ID, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03B 5/32

US Classification:

331158, 331 16, 331 36 C, 331116 R, 331175, 331179, 331182, 331183

Abstract:

Described is a circuit comprising an oscillator, an amplifier unit and a control unit. The amplifier unit is coupled to the oscillator and to the control unit; and the control unit is arranged to regulate a load capacitance to the oscillator at startup.

US Patent:

8085100, Dec 27, 2011

Filed:

Feb 19, 2008

Appl. No.:

12/070547

Inventors:

Aaron Brennan - Moscow ID, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03B 27/00

US Classification:

331 45, 333172

Abstract:

A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

US Patent:

6704901, Mar 9, 2004

Filed:

Jul 11, 2000

Appl. No.:

09/613471

Inventors:

Torkjell Berge - Moscow ID
Aaron James Brennan - Deary ID

Assignee:

AMI Semiconductor, Inc. - Pocatello ID

International Classification:

H03M 1300

US Classification:

714784, 708492

Abstract:

A runtime programable RS decoder that can operate on multiple pieces of data during one clock cycle in order to generate, reduce, and evaluate polynomials involved in the decoding of an RS code, and which allows a user to choose the RS code after the circuit has been implemented.