Aaron K Martin

US Patent:

6348826, Feb 19, 2002

Filed:

Jun 28, 2000

Appl. No.:

09/605624

Inventors:

Stephen R. Mooney - Beaverton OR
Matthew B. Haycock - Beaverton OR
Aaron K. Martin - Hillsboro OR
Jonathan N. Spitz - Portland OR
Michael S. Sandhinti - Olympia WA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03H 1116

US Classification:

327270, 327231

Abstract:

A variable-delay circuit on an integrated circuit is used to delay a periodic strobe signal. In normal operation, the strobe signal can be shifted 90 degrees to center it within a data bit cell. In test mode, it can also be shifted up to 270 degrees in N increments to measure the effective input latch setup and hold timings. The variable-delay circuit comprises a voltage-mixing interpolator circuit to produce phase delays in N increments. The variable-delay circuit can incorporate an existing delay locked loop. Also described are an electronic system, a data processing system, and various methods of performing on-chip testing and calibration.

US Patent:

6373289, Apr 16, 2002

Filed:

Dec 26, 2000

Appl. No.:

09/752895

Inventors:

Aaron K. Martin - Hillsboro OR
Stephen R. Mooney - Beaverton OR
Joseph T. Kennedy - Beaverton OR
Matthew B. Haycock - Beaverton OR
Shekhar Y. Borkar - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1900

US Classification:

326 93, 326 95, 326 98, 375376, 327141

Abstract:

A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

US Patent:

6377108, Apr 23, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649257

Inventors:

Joseph T. Kennedy - Beaverton OR
Stephen R. Mooney - Beaverton OR
Aaron K. Martin - Hillsboro OR
Rajendran Nair - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1776

US Classification:

327407, 327 99

Abstract:

A differential amplifier is provided, incorporating negative hysteresis by automatic reference voltage adjustment. A delayed output signal is routed to a switch or multiplexer which functions to select one of two reference voltage levels, creating negative hysteresis. The delayed output signal is delayed by a series of inverters, which prevent certain embodiments of the invention from oscillating under some conditions. The two reference voltage levels are selected to be near the respective data signal input high and low signal voltage levels, but far enough from these levels so as not to be adversely affected by noise or other interference.

US Patent:

6437601, Aug 20, 2002

Filed:

Dec 26, 2000

Appl. No.:

09/752906

Inventors:

Shekhar Y. Borkar - Beaverton OR
Matthew B. Haycock - Beaverton OR
Stephen R. Mooney - Beaverton OR
Aaron K. Martin - Hillsboro OR
Joseph T. Kennedy - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19096

US Classification:

326 93, 326 9, 326 21

Abstract:

In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

US Patent:

6441649, Aug 27, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/752647

Inventors:

Aaron K. Martin - Hillsboro OR
Stephen R. Mooney - Beaverton OR
Joseph T. Kennedy - Beaverton OR
Matthew B. Haycock - Beaverton OR
Shekhar Y. Borkar - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 1900

US Classification:

327 52, 327 57

Abstract:

The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.

US Patent:

6445170, Sep 3, 2002

Filed:

Oct 24, 2000

Appl. No.:

09/694901

Inventors:

Amaresh Pangal - Hillsboro OR
Siva G. Narendra - Beaverton OR
Aaron K. Martin - Hillsboro OR
Stephen R. Mooney - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 156

US Classification:

323315, 323317

Abstract:

A current reference with reduced sensitivity to process variations includes two current sources. The first current source has an output current that is sensitive to process variations. The second current source has, as a component of its input current, the output current of the first current source. The input current to the second current source is substantially constant because the process dependent component has been removed by the output current of the first current source. Variable resistors internal to the current source are set using a control loop circuit and an external resistor.

US Patent:

6501256, Dec 31, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/897792

Inventors:

James E. Jaussi - Hillsboro OR
Stephen R. Mooney - Beaverton OR
Aaron K. Martin - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 316

US Classification:

323315, 323316

Abstract:

A trimmable bandgap voltage reference circuit includes variable current sources to drive variable currents through parallel combination circuits. The parallel combination circuits include variable resistors and diodes of differing sizes. Voltages developed across the parallel combination circuits are input to a differential amplifier that is used as a feedback amplifier to bias the variable current sources. The variable current sources and variable resistors can all be digitally controlled. A processor can query the operating point of the bandgap voltage reference circuit, and can also set the current and resistance values through a control circuit.

US Patent:

6507225, Jan 14, 2003

Filed:

Apr 16, 2001

Appl. No.:

09/835600

Inventors:

Aaron K. Martin - Hillsboro OR
Stephen R. Mooney - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 300

US Classification:

327108, 327404

Abstract:

A simultaneous bidirectional data port circuit includes a current mode output driver for driving an output node and a current mode return driver for driving a differential receiver. The current mode return driver is scalable to reduce current requirements. Each driver is divided into driver segments. Some driver segments are driven by outbound data, and other driver segments are driven by pre-equalization data. Variable pre-equalization is provided by a pre-driver that selects the number of driver segments to be driven with pre-equalization data and the number of driver segments to be driven by outbound data.