Abha S Kasper

age ~61

from Dallas, TX

Also known as:
  • Abha J Kasper
  • Abha R Singh
  • Abba R Singh
  • Adha Singh
Phone and address:
4540 Ridgeside Dr, Dallas, TX 75244
4699141051

Abha Kasper Phones & Addresses

  • 4540 Ridgeside Dr, Dallas, TX 75244 • 4699141051
  • Fairview, TX
  • Garland, TX
  • Carrollton, TX
  • Stony Brook, NY
  • Austin, TX
  • 701 Forest Oaks Dr, Mc Kinney, TX 75069

Work

  • Company:
    Texas instruments
    2006
  • Position:
    Low power cmos product engineering manager; senior member technical staff

Education

  • Degree:
    Master of Science
  • School / High School:
    IIT Delhi
  • Specialities:
    Physics

Skills

Cmos • Semiconductors • Product Engineering • Ic • Silicon • Semiconductor Industry • Process Integration • Soc • Mixed Signal • Asic • Dft • Failure Analysis • Vlsi • Yield • Microelectronics • Power Management • Analog Circuit Design • Device Characterization • Static Timing Analysis • Microprocessors

Industries

Semiconductors

Resumes

Abha Kasper Photo 1

Cmos Product Engineering Manager; Distinguished Member Technical Staff

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments since 2006
Low Power CMOS Product Engineering Manager; Senior Member Technical Staff

Texas Instruments - Dallas, Texas 2000 - 2005
90nm Interconnect Integration Manager

STMicroelectronics - Dallas/Fort Worth Area 1993 - 1995
Senior Process Engineer
Education:
IIT Delhi
Master of Science, Physics
IIT Kanpur
Master of Technology (MTech), Materials Science
SUNY Stony Brook
Doctor of Philosophy (Ph.D.), Materials Science and Engineering
Skills:
Cmos
Semiconductors
Product Engineering
Ic
Silicon
Semiconductor Industry
Process Integration
Soc
Mixed Signal
Asic
Dft
Failure Analysis
Vlsi
Yield
Microelectronics
Power Management
Analog Circuit Design
Device Characterization
Static Timing Analysis
Microprocessors

Us Patents

  • Methods And Devices For Determining Logical To Physical Mapping On An Integrated Circuit

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  • US Patent:
    20130329508, Dec 12, 2013
  • Filed:
    Jun 7, 2012
  • Appl. No.:
    13/491429
  • Inventors:
    Stanton Petree Ashburn - McKinney TX, US
    Daniel L. Corum - Richardson TX, US
    Abha Singh Kasper - Fairview TX, US
    Harold C. Waite - Rockwall TX, US
    Eric D. Rullan - Allen TX, US
    Donald L. Plumton - Dallas TX, US
    Douglas A. Prinslow - McKinney TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    G11C 29/00
    H01L 21/02
  • US Classification:
    365200, 438 4, 257E21002
  • Abstract:
    Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.
  • Multi-Channel Mcm With Test Circuitry For Inter-Die Bond Wire Checking

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  • US Patent:
    20170194285, Jul 6, 2017
  • Filed:
    May 25, 2016
  • Appl. No.:
    15/164608
  • Inventors:
    - Dallas TX, US
    ZHUANG MA - BEIJING, CN
    XINYU YIN - BEIJING, CN
    MICHAEL DEAN SHILHANEK - GARLAND TX, US
    STEVEN BOLEN - PLANO TX, US
    ALBERT EARDLEY - CARRIZO SPRINGS TX, US
    ABHA SINGH KASPER - DALLAS TX, US
  • International Classification:
    H01L 23/00
    G01R 31/04
    H01L 21/66
  • Abstract:
    A multichip module (MCM) device include a first die including functional circuitry bonded by a plurality of inter-die bond wires (bond wires) to a second die having functional circuitry. A first channel (Channel A) and second channel (Channel B) each have separate top and bottom signal paths (signal paths) including one of the bond wires. A failure of any of the signal paths does not affect functionality of the device. The first die includes input pins including a first input pin (P), a second input pin (P), and coupling circuitry including cross-channel test circuitry positioned between the input pins and the functional circuitry. The coupling circuitry provides for Channel A and Channel B a first configuration for normal mode operation and a second configuration for test mode operation for single bond wire testing for checking continuity of any of the bond wires.
  • Methods And Devices For Determining Logical To Physical Mapping On An Integrated Circuit

    view source
  • US Patent:
    20160245861, Aug 25, 2016
  • Filed:
    Mar 2, 2016
  • Appl. No.:
    15/058263
  • Inventors:
    - Dallas TX, US
    Abha Singh Kasper - Dallas TX, US
    Harold C. Waite - Rockwall TX, US
    Eric D. Rullan - Allen TX, US
    Donald L. Plumton - Dallas TX, US
    Douglas A. Prinslow - McKinney TX, US
  • International Classification:
    G01R 31/317
    G01R 31/3177
    H01L 27/02
    G01R 31/28
  • Abstract:
    Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.
  • Memory Repair Categorization Tracking

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  • US Patent:
    20150279487, Oct 1, 2015
  • Filed:
    Mar 26, 2014
  • Appl. No.:
    14/226700
  • Inventors:
    - Dallas TX, US
    Stanton Petree Ashburn - McKinney TX, US
    Abha Singh Kasper - Fairview TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    G11C 29/44
    G11C 17/18
    G11C 29/00
    G11C 17/16
  • Abstract:
    An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.

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