Adam R Talcott

US Patent:

6510511, Jan 21, 2003

Filed:

Jun 26, 2001

Appl. No.:

09/888440

Inventors:

Adam R. Talcott - San Jose CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 938

US Classification:

712240, 712239

Abstract:

A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.

US Patent:

6615343, Sep 2, 2003

Filed:

Jun 22, 2000

Appl. No.:

09/599227

Inventors:

Adam R. Talcott - San Jose CA
Daniel L. Liebholz - Cambridge MA
Sanjay Patel - Fremont CA
Richard H. Larson - Los Gatos CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 938

US Classification:

712244

Abstract:

A method of handling an exception in a processor includes setting a state upon detection of an exception, signaling a trap for the exception if the state is set, and based on a class of the exception, processing the exception differently before signaling the trap. The method may include replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception. The method may include replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction. The method may include signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction. The method may include marking an instruction causing the exception as complete without issuing the instruction causing the exception. An apparatus for handling exceptions in a processor includes an instruction scheduler for setting a state upon detection of an exception and signaling a trap for the exception if the state is set.

US Patent:

6738897, May 18, 2004

Filed:

Oct 6, 2000

Appl. No.:

09/680840

Inventors:

Adam R. Talcott - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 938

US Classification:

712240, 712239

Abstract:

A method for improving prediction of an outcome for a branch instruction in a set of instructions includes storing local branch history data for the branch instruction, using the local branch history data to predict the outcome of the branch instruction, and speculatively updating the local branch history data with the predicted outcome of the branch instruction. An apparatus for improving prediction of an outcome for a branch instruction in a set of instructions includes a memory for storing local branch history data for the branch instruction and a processor for using the local branch history data to predict the outcome of the branch instruction and speculatively updating the local branch history data with the predicted outcome of the branch instruction.

US Patent:

6934830, Aug 23, 2005

Filed:

Sep 26, 2002

Appl. No.:

10/259721

Inventors:

Sudarshan Kadambi - Hayward CA, US
Adam R. Talcott - San Jose CA, US
Wayne I. Yamamoto - Saratoga CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F009/30

US Classification:

712214, 711125, 712219

Abstract:

One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.

US Patent:

6948055, Sep 20, 2005

Filed:

Oct 9, 2000

Appl. No.:

09/685270

Inventors:

Adam R. Talcott - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F009/38

US Classification:

712239

Abstract:

A method and apparatus of improving prediction accuracy of a branch instruction scheme includes reading an individual instruction in a current set of instructions, fetching the individual instruction when an instruction fetch unit determines that the individual instruction is valid, and allowing the instruction fetch unit to use an index address for the fetched individual instruction. A method and apparatus of improving branch prediction accuracy includes receiving a set of instructions having an assigned address, making a prediction for a branch instruction in the set of instructions using the assigned address, and retaining the assigned address for the branch instruction in the set of instructions.

US Patent:

7096390, Aug 22, 2006

Filed:

Apr 1, 2002

Appl. No.:

10/113357

Inventors:

Adam Talcott - San Jose CA, US
Mario Wolczko - San Carlos CA, US

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 11/00

US Classification:

714 45, 714 47, 712227, 717127

Abstract:

A sampling mechanism is disclosed in which software can specify a property or properties which characterize samples of interest. For example, if the software is interested in cache behavior, the software can specify that information for memory operations, or only information for memory instructions which miss in one or more caches, be reported. The sampling mechanism may specify many such properties and events (properties and events may vary from processor to processor, and may also depend on which properties or events are considered useful for performance analysis).

US Patent:

7707554, Apr 27, 2010

Filed:

Jun 30, 2004

Appl. No.:

10/880485

Inventors:

Nicolai Kosche - San Francisco CA, US
Robert E. Cypher - Saratoga CA, US
Mario I. Wolczko - San Carlos CA, US
John P. Petry - San Diego CA, US
Adam R. Talcott - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 9/44

US Classification:

717127, 717130, 717131, 714 38, 714 47, 712227

Abstract:

Associating data source information with sampled runtime events allows identification of system components related to the sampled runtime events. Code can be optimized from the perspective of system components and for various architectures. A system provides a data source indication. The system associates the data source indication with a corresponding instruction instance. The instruction instance is related to a sampled runtime event, and the sampled runtime event is associated with the data source indication. The data source information and associated sampled runtime event can be supplied for profiling code.

US Patent:

7809895, Oct 5, 2010

Filed:

Mar 9, 2007

Appl. No.:

11/684348

Inventors:

Lawrence A. Spracklen - Boulder Creek CA, US
Adam R. Talcott - Los Altos CA, US
Santosh G. Abraham - Pleasanton CA, US
Sothea Soun - Palo Alto CA, US
Sanjay Patel - Fremont CA, US
Farnad Sajjadian - Sunnyvale CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 12/14
G06F 13/00
G06F 15/82

US Classification:

711151, 711163, 710 36, 712 34

Abstract:

In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.