Ahmed I Syed

US Patent:

7203875, Apr 10, 2007

Filed:

May 7, 2004

Appl. No.:

10/841019

Inventors:

Ahmed Rashid Syed - Santa Clara CA, US

Assignee:

Credence Systems Corporation - Milpitas CA

International Classification:

G01R 31/317
G01R 31/333

US Classification:

714724, 714700, 714 55

Abstract:

The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.

US Patent:

7242257, Jul 10, 2007

Filed:

May 7, 2004

Appl. No.:

10/840850

Inventors:

Ahmed Rashid Syed - Santa Clara CA, US

Assignee:

Credence Systems Corporation - Milpitas CA

International Classification:

H03K 3/03

US Classification:

331 57, 331 74, 324765, 713503

Abstract:

The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides an auto-calibration system. The system includes: a plurality of delay line elements (DLEs) adapted to be connected in a loop; a state machine coupled to the plurality of DLEs and operative to provide state data for the plurality of DLEs; a start oscillation signal receiving circuit coupled to the loop and operative to trigger the loop in response to receipt of a start oscillation signal; and a calibration circuit coupled to the loop and operative to acquire calibration data for the plurality of DLEs.

US Patent:

7266739, Sep 4, 2007

Filed:

May 7, 2004

Appl. No.:

10/840898

Inventors:

Ahmed Rashid Syed - Santa Clara CA, US

Assignee:

Credence Systems Solutions - Milpitas CA

International Classification:

G01R 31/3183
G01R 31/3173

US Classification:

714724, 714744

Abstract:

The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a test system formatter including: a plurality of event logic interfaces, each event logic interface capable of receiving and decoding timing signals; a plurality of delay line elements (DLEs), each DLE being coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from the corresponding event logic interface; drive logic coupled to the plurality of DLEs, having first and second outputs and operative to produce first and second formatted levels on the first and second outputs in response to timing markers received from the plurality of DLEs; response logic coupled to the plurality of DLEs, having first and second inputs and operative to produce strobe markers in response to timing markers received from the plurality of DLEs; and a loop-back circuit.

US Patent:

7765443, Jul 27, 2010

Filed:

May 7, 2004

Appl. No.:

10/840851

Inventors:

Ahmed Rashid Syed - Santa Clara CA, US
Burnell G. West - Half Moon Bay CA, US

Assignee:

Credence Systems Corporation - Milpitas CA

International Classification:

G01R 31/28

US Classification:

714724, 714700, 714701, 714742

Abstract:

One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.

US Patent:

51954699, Mar 23, 1993

Filed:

Aug 13, 1991

Appl. No.:

7/744561

Inventors:

Ahmed Syed - Los Angeles CA

International Classification:

F02B 7504

US Classification:

123 48A

Abstract:

An improved arrangement for controlling and adjusting the compression ratio of an internal combustion engine (10) during operation. A secondary cylinder (201) is formed in the engine cylinder head (102) and opens upon the combustion chamber (110) of the engine. A secondary piston (203) is positioned by a control device (503) within the secondary cylinder (201). The rear most position corresponding to the lowest compression ratio. The desired position of the secondary piston (203), that compression ratio which corresponds to maximum efficiency of the engine, is controlled by a logic unit (816) operating upon such inputs as the engine load as correlated to the input manifold pressure, the engine RPM and the present position of the secondary piston (203). The linkage of the control may utilize a servo motor or hydraulic driver to rotate a shaft (301). All secondary pistons (203) may be operated in unison or a control system may be provided for each cylinder (201).

US Patent:

20180267257, Sep 20, 2018

Filed:

Jun 30, 2017

Appl. No.:

15/638988

Inventors:

- Singapore, SG
Faouzi Chaahoub - San Jose CA, US
Ahmed Rashid Syed - San Jose CA, US
Kartikeya Gupta - San Jose CA, US
Kazi Asaduzzaman - Union City CA, US

International Classification:

G02B 6/38
G02B 6/42
H01S 5/068
H04B 10/50
H04B 10/516

Abstract:

A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.