Ahsan Habib Chowdhury

US Patent:

7158045, Jan 2, 2007

Filed:

Mar 24, 2005

Appl. No.:

11/088446

Inventors:

Daniel Gudmunson - Dripping Springs TX, US
John Melanson - Austin TX, US
Rahul Singh - Austin TX, US
Ahsan Chowdhury - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H04L 7/00

US Classification:

34082521, 340 32, 340536, 341 61, 375356, 348497

Abstract:

A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.

US Patent:

7339628, Mar 4, 2008

Filed:

Oct 13, 2004

Appl. No.:

10/964547

Inventors:

Daniel Gudmondson - Austin TX, US
John L. Melanson - Austin TX, US
Rahul Singh - Austin TX, US
James A. Antone - Austin TX, US
Ahsan Habib Chowdhury - Austin TX, US
Krishnan Subramoniam - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03M 1/12

US Classification:

348572, 348441, 348505, 348544, 348571

Abstract:

Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

US Patent:

7355652, Apr 8, 2008

Filed:

Oct 13, 2004

Appl. No.:

10/964556

Inventors:

Daniel Gudmondson - Austin TX, US
John L. Melanson - Austin TX, US
Rahul Singh - Austin TX, US
Ahsan Habib Chowdhury - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03L 7/00

US Classification:

348536, 348537, 348441, 348445

Abstract:

A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by transferring the digitized video signal, sampled with an asynchronous crystal clock, into the source clock domain, the accuracy of the brightness (amplitude) and color (phase) information can be greatly enhanced.

US Patent:

7400362, Jul 15, 2008

Filed:

Dec 16, 2004

Appl. No.:

11/015756

Inventors:

Daniel Gudmundson - Austin TX, US
Shyam Somayajula - Austin TX, US
Ahsan Habib Chowdhury - Austin TX, US
James A. Antone - Austin TX, US
Rahul Singh - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H04N 7/01
G05F 1/40

US Classification:

348607, 323280

Abstract:

A system in which drooping of the video levels due to leakage currents and proper DC bias level is addressed by providing a charge into the video signal to offset the leakage currents and to provide DC bias. To determine the leakage current level, measurements are made measuring the voltages of the syncs and the blanking intervals. To determine the DC bias, a measurement is made of the sync. Over a series of video lines these measurements are averaged. If the average is below the desired level, a charge is provided via a current source to the incoming signal. By having the current source provide charge during each video line, droop is reduced and the proper DC bias is provided.

US Patent:

7471340, Dec 30, 2008

Filed:

Mar 24, 2005

Appl. No.:

11/088447

Inventors:

Ahsan Chowdhury - Austin TX, US
Rahul Singh - Austin TX, US
John L. Melanson - Austin TX, US
James A. Antone - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03M 1/12
H03L 7/00
H04N 9/64

US Classification:

348572, 348536, 348714

Abstract:

A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selectable decimation factor prior to buffering. By selecting different decimation factors, the effective length of the buffer is changed from short duration for stable input signals and to longer duration for unstable input signals. A video signal quality detector is employed to provide a selection input that adjusts the decimation factor and also the loop bandwidth of a clock generator that provides the output clock for the buffer, which is generated from the input signal via a phase-lock loop (PLL). The operation of the system automatically varies from highly responsive for stable video input signals to less responsive for unstable video input signals, providing improved stability in the video output.

US Patent:

7474724, Jan 6, 2009

Filed:

Mar 17, 2005

Appl. No.:

11/082347

Inventors:

Daniel Gudmunson - Dripping Springs TX, US
John Melanson - Austin TX, US
Rahul Singh - Austin TX, US
Ahsan Chowdhury - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03D 3/24

US Classification:

375376

Abstract:

A method and system for video-synchronous audio clock generation from an asynchronously sampled video signal provides a mechanism for maintaining synchronization of audio sampling in digital video-audio systems. A ratio between the sampling clock frequency and an audio reference frequency clock is computed via an all digital phase-lock loop (ADPLL) and an audio clock is generated from the ratio by another PLL or a number to clock converter. In systems where a sampling clock to source video clock ratio has been computed for recovering a video signal, the audio ratio can be computed directly from the video ratio.

US Patent:

7499106, Mar 3, 2009

Filed:

Mar 17, 2005

Appl. No.:

11/082346

Inventors:

Daniel Gudmunson - Dripping Springs TX, US
John Melanson - Austin TX, US
Rahul Singh - Austin TX, US
Ahsan Chowdhury - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H04L 7/00

US Classification:

348536, 348537, 348547

Abstract:

A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.

US Patent:

20060044468, Mar 2, 2006

Filed:

Jan 24, 2005

Appl. No.:

11/041582

Inventors:

Ahsan Chowdhury - Austin TX, US
James Antone - Austin TX, US
Krishnan Subramoniam - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H04N 11/00

US Classification:

348465000

Abstract:

A single-chip video decoder includes a primary data path for capturing and slicing vertical blanking interval information carried by a primary channel of video data received by a video decoder. Power control circuitry is operable during an inactive period of the video decoder to activate the primary data path during vertical blanking intervals of the received primary channel of video data for capturing and slicing the vertical blanking interval data; and to deactivate the primary data path between the vertical blanking interval and a subsequent vertical blanking interval of the received primary channel of video data to reduce power consumption. According to further inventive concepts, analog and/or digital circuitry which is unnecessary for capturing and slicing the vertical blanking information, including data paths processing secondary channels of video data, is deactivated during substantially the entire inactive period of the video decoder. In an additional embodiment, the input/output ports of the video decoder are set into a static state for substantially the entire inactive period.