Akshay K Mangrulkar

Senior Component Design Engineer

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Location:

2903 Bunker Hill Ln, Santa Clara, CA 95054

Industry:

Semiconductors

Work:

Netronome - Greater Boston Area since Apr 2012
Logic Design Engineer
Arasan Chip Systems Inc., - San Jose Jul 2011 - Apr 2012
IP Design/Verification Engineer
San Jose State University - San Jose State Unviersity Jun 2010 - Dec 2011
Computer Lab Assistant
San Jose State University Aug 2009 - Dec 2011
Graduate Student
Silicon Image Aug 2010 - Dec 2010
IP Digital Design Intern

Education:

San Jose State University 2009 - 2011
Master, Electrical Engineering, Digital Design Nagpur University 2003 - 2007
Bachelors of Engineering, Electronics Somalwar High School 1991 - 2001
HSSC

Skills:

Verilog
Asic
Systemverilog
C
Integrated Circuit Design
Perl
Cadence Virtuoso
Logic Design
Electronics
Vlsi
Vhdl
Testing
C++
Rtl Design
Circuit Design
Xilinx
Veritas Cluster Server
Digital Hardware Design
Electrical Engineering
Digital Design
Matlab
Digital Electronics
Ahb
Mixed Signal
Vcs
Simulink
Rtl Coding
Hardware Design
Ncsim
Network Design
Pcie
Serdes
Jtag
Ddr3
Mbist
Application Specific Integrated Circuits
Ovm
Universal Verification Methodology
Ddr
Dynamic Random Access Memory
Mixed Signal Ic Design
Analog Circuit Design

Akshay Mangrulkar

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