Alan David Armstrong

US Patent:

7379452, May 27, 2008

Filed:

Dec 21, 2001

Appl. No.:

10/028871

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

7885255, Feb 8, 2011

Filed:

May 23, 2008

Appl. No.:

12/126188

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Lake Cherokee Hard Drive Technologies, LLC - Longview TX

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

7957370, Jun 7, 2011

Filed:

May 23, 2008

Appl. No.:

12/126188

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Lake Cherokee Hard Drive Technologies, LLC - Longview TX

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

60210117, Feb 1, 2000

Filed:

Mar 19, 1997

Appl. No.:

8/822603

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan J. Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill R. Foland - Littleton CO
Neal Glover - Broomfield CO
Larry D. King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509

US Classification:

360 51

Abstract:

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

US Patent:

54248817, Jun 13, 1995

Filed:

Feb 1, 1993

Appl. No.:

8/012266

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill Foland - Littleton CO
Neal Glover - Broomfield CO
Larry King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509
G11B 2014
G11B 2016
G06F 1110

US Classification:

360 40

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

56233779, Apr 22, 1997

Filed:

Apr 4, 1994

Appl. No.:

8/222666

Inventors:

Richard T. Behrens - Louisville CO
Neal Glover - Broomfield CO
Trent O. Dudley - Littleton CO
Alan J. Armstrong - Broomfield CO
Christopher P. Zook - Longmont CO
William G. Bliss - Thornton CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 5035
G11B 509

US Classification:

360 65

Abstract:

A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput. Further, the pre-cursor correcting portion of the filter can be disabled in order to avoid delaying the data stream while still canceling the post-cursor secondary pulses.

US Patent:

60057319, Dec 21, 1999

Filed:

Apr 18, 1997

Appl. No.:

8/844174

Inventors:

William R. Foland - Littleton CO
Richard T. Behrens - Lafayette CO
Alan J. Armstrong - Pleasanton CA
Neal Glover - Broomfield CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509

US Classification:

360 53

Abstract:

A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons.

US Patent:

58123342, Sep 22, 1998

Filed:

Mar 16, 1994

Appl. No.:

8/210302

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill Foland - Littleton CO
Neal Glover - Broomfield CO
Larry King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509

US Classification:

360 40

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.