Alan S Baker

US Patent:

47663677, Aug 23, 1988

Filed:

Jul 20, 1987

Appl. No.:

7/075140

Inventors:

Kenneth R. Saller - Fort Collins CO
Alan J. Baker - Fort Collins CO
Steven O. Smith - Fort Collins CO

Assignee:

Comlinear Corporation - Fort Collins CO

International Classification:

G05F 326

US Classification:

323315

Abstract:

An improved current mirror is described which has utility as either a stand alone current source or as a gain block whenever current gain or transimpedance gain is required. When used as a current source the current mirror exhibits higher output impedance, and when used as a gain block, the current mirror exhibits improved higher frequency performance and high transimpedance gain than prior art current mirrors.

US Patent:

59735120, Oct 26, 1999

Filed:

Dec 2, 1997

Appl. No.:

8/982959

Inventors:

Alan J. Baker - Loveland CO

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 1903
H03K 1994

US Classification:

326 87

Abstract:

n A buffer having an output slew rate which is relatively insensitive to loading and supply voltage. The output buffer includes an output node, a first half-circuit and a second half-circuit. The first half-circuit is for slewing the output node from a first voltage to a second voltage. The first half-circuit includes a first output transistor connected between the output node and a second voltage reference node, a first switching device connected from a gate of the first output transistor to the second voltage reference node, a second switching device connected from the gate of the output transistor to a first node, a first current source connected from a first voltage reference node to the first node, and a first capacitor connected from the output node to the first node. The second half-circuit is for slewing the output node from the second voltage to the first voltage. The second half-circuit includes a second output transistor connected between the output node and the first voltage reference node, a third switching device connected from the gate of the second output transistor to the first voltage reference node, a fourth switching device connected from the gate of the second output transistor to a second node, a second current source connected from the second voltage reference node to the second node, and a second capacitor connected from the output node to the second node.

US Patent:

59784172, Nov 2, 1999

Filed:

Sep 13, 1996

Appl. No.:

8/713626

Inventors:

Alan J. Baker - Loveland CO
Marc H. Ryat - Santa Clara CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03H 730
H03H 500
G03G 1104
G06F 1710

US Classification:

375232

Abstract:

An adaptive cable equalizer is provided with a simple architecture, wherein a single control structure: controls the adaptation of the filter for compensating for cable length while simultaneously compensating for process and temperature variations; optimizes the SNR at any cable length by controlling biasing current sources; and uses a two-stage architecture which eliminates start-up problems and optimizes output levels to obtain optimal dc restoration while simultaneously allowing for independent optimization of the output levels of the recovered data in accordance with other requirements as desired. An analog adaptive equalizing filter is used for accurately synthesizing the inverse transfer function of cables of variable lengths. Data rates up to and beyond 400 Mbps are supported and the adaptive behavior automatically compensates for different cable lengths as well as process variations (with respect to the process(es) used for fabricating the equalizer in a monolithic form) and temperature variations.