Alan J Drake

US Patent:

7321269, Jan 22, 2008

Filed:

Jul 19, 2005

Appl. No.:

11/184352

Inventors:

Alan J. Drake - Round Rock TX, US
Fadi H. Gebara - Austin TX, US
Jeremy D. Schaub - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/03
H03B 27/00

US Classification:

331 57, 331 45, 331183

Abstract:

An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.

US Patent:

7415645, Aug 19, 2008

Filed:

Jul 28, 2005

Appl. No.:

11/191655

Inventors:

Alan J. Drake - Round Rock TX, US
AJ Klein Osowski - Austin TX, US
Andrew K. Martin - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714724

Abstract:

A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.

US Patent:

7418641, Aug 26, 2008

Filed:

Oct 3, 2005

Appl. No.:

11/242491

Inventors:

Alan J. Drake - Round Rock TX, US
Aj KleinOsowski - Austin TX, US
Andrew K. Martin - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G06F 11/08

US Classification:

714726, 714797

Abstract:

A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).

US Patent:

7542862, Jun 2, 2009

Filed:

May 18, 2007

Appl. No.:

11/750475

Inventors:

Harmander Singh - Austin TX, US
Alan J. Drake - Round Rock TX, US
Fadi H. Gebara - Austin TX, US
John P. Keane - Minneapolis MN, US
Jeremy D. Schaub - Austin TX, US
Robert M. Senger - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 29/02
G01R 29/00
G01R 35/00
G01D 18/00
G01P 21/00

US Classification:

702 89, 702 79, 702 80

Abstract:

A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

US Patent:

7548823, Jun 16, 2009

Filed:

May 18, 2007

Appl. No.:

11/750385

Inventors:

Harmander Singh - Austin TX, US
Alan J. Drake - Round Rock TX, US
Fadi H. Gebara - Austin TX, US
John P. Keane - Minneapolis MN, US
Jeremy D. Schaub - Austin TX, US
Robert M. Senger - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 29/00

US Classification:

702 79, 700306, 702 57, 702136

Abstract:

Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.

US Patent:

7576569, Aug 18, 2009

Filed:

Oct 13, 2006

Appl. No.:

11/549138

Inventors:

Gary D. Carpenter - Austin TX, US
Alan J. Drake - Round Rock TX, US
Harmander S. Deogun - Austin TX, US
Michael S. Floyd - Austin TX, US
Norman K. James - Liberty Hill TX, US
Robert M. Senger - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 29/02
G06F 17/50
H03K 5/22

US Classification:

327 14, 327 24, 716 14, 716 18

Abstract:

A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e. g. , NBTI, hot electrons).

US Patent:

7590907, Sep 15, 2009

Filed:

Jul 6, 2008

Appl. No.:

12/168147

Inventors:

Alan J. Drake - Round Rock TX, US
AJ KleinOsowski - Austin TX, US
Andrew K. Martin - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.

US Patent:

7667513, Feb 23, 2010

Filed:

Nov 12, 2004

Appl. No.:

10/988454

Inventors:

Gary D. Carpenter - Austin TX, US
Alan J. Drake - Round Rock TX, US
Fadi H. Gebara - Austin TX, US
Chandler T. McDowell - Austin TX, US
Hung C. Ngo - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/017

US Classification:

327175, 327172

Abstract:

A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.