Alan A Fitzgerald

US Patent:

7925847, Apr 12, 2011

Filed:

Jun 6, 2008

Appl. No.:

12/134683

Inventors:

Robert W Ellis - Phoenix AZ, US
Alan A Fitzgerald - Gilbert AZ, US
Daniel P Fogelson - Chandler AZ, US
Kevin Lee Kilzer - Chandler AZ, US

Assignee:

Adtron Corporation - Phoenix AZ

International Classification:

G06F 12/00
G06F 13/32

US Classification:

711154, 710 23, 710 27, 711114

Abstract:

A storage system controller () includes a plurality of media controllers (), a local microprocessor (), and a host interface logic (), operably coupled by a multi-drop bus. The multi-drop bus includes a control bus (), a payload data bus (), a real-time ready-status (data ready) signaling bus () and a general microprocessor bus (). Each media controller has a storage media () operably coupled thereto. Each media controller includes a parameter storage (), a media interface circuit (), a control data state machine (), a command sequencer state machine (), a media-side multi-mode transfer state machine (), a dual-port memory (), a memory controller (), and a host-side transfer state machine (). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command.

US Patent:

20030212859, Nov 13, 2003

Filed:

Aug 12, 2002

Appl. No.:

10/217167

Inventors:

Robert Ellis - Phoenix AZ, US
Kevin Kilzer - Chandler AZ, US
Daniel Fogelson - Chandler AZ, US
Alan Fitzgerald - Gilbert AZ, US

International Classification:

G06F012/00

US Classification:

711/114000, 711/154000, 711/131000

Abstract:

A storage system controller () includes a plurality of media controllers (), a local microprocessor (), and a host interface logic (), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus (), a payload data bus (), a real-time ready-status (data ready) signaling bus () and a general microprocessor bus (). Each media controller has a storage media () operably coupled thereto. Each media controller includes a parameter storage (), a media interface circuit (), a control data state machine (), a command sequencer state machine (), a media-side multi-mode transfer state machine (), a dual-port memory (), a memory controller (), and a host-side transfer state machine (). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation.

US Patent:

20050132040, Jun 16, 2005

Filed:

Jan 26, 2005

Appl. No.:

11/043709

Inventors:

Robert Ellis - Phoenix AZ, US
Kevin Kilzer - Chandler AZ, US
Daniel Fogelson - Chandler AZ, US
Alan Fitzgerald - Gilbert AZ, US

International Classification:

G11B003/00

US Classification:

709223000

Abstract:

A storage system controller () includes a plurality of media controllers (), a local microprocessor (), and a host interface logic (), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus (), a payload data bus (), a real-time ready-status (data ready) signaling bus () and a general microprocessor bus (). Each media controller has a storage media () operably coupled thereto. Each media controller includes a parameter storage (), a media interface circuit (), a control data state machine (), a command sequencer state machine (), a media-side multi-mode transfer state machine (), a dual-port memory (), a memory controller (), and a host-side transfer state machine (). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation.

US Patent:

20060044899, Mar 2, 2006

Filed:

Aug 26, 2005

Appl. No.:

11/212173

Inventors:

Robert Ellis - Phoenix AZ, US
Alan Fitzgerald - Gilbert AZ, US
Daniel Fogelson - Chandler AZ, US
Kevin Kilzer - Chandler AZ, US

International Classification:

G11C 29/00

US Classification:

365201000

Abstract:

On command and subject to a fail-safe interlock, a signal is generated to essentially instantaneously destroy the data and/or access to data stored in a flash memory device. Subsequently, the storage memory device is tested for confirmation of destruction of the data and/or access to the data. This cycle is repeated until verification of destruction of the data and/or access to data is achieved.

US Patent:

20090259800, Oct 15, 2009

Filed:

Apr 15, 2008

Appl. No.:

12/103273

Inventors:

Kevin L. Kilzer - Chandler AZ, US
Robert W. Ellis - Phoenix AZ, US
Alan A. Fitzgerald - Gilbert AZ, US
Rudolph J. Sterbenz - Chandler AZ, US

Assignee:

ADTRON, INC. - Phoenix AZ

International Classification:

G06F 12/02

US Classification:

711103, 711E12008

Abstract:

Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device.

US Patent:

20090259801, Oct 15, 2009

Filed:

Apr 15, 2008

Appl. No.:

12/103277

Inventors:

Kevin L. Kilzer - Chandler AZ, US
Robert W. Ellis - Phoenix AZ, US
Alan A. Fitzgerald - Gilbert AZ, US
Rudolph J. Sterbenz - Chandler AZ, US

Assignee:

ADTRON, INC. - Phoenix AZ

International Classification:

G06F 12/02

US Classification:

711103, 711E12008

Abstract:

A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

US Patent:

20110035540, Feb 10, 2011

Filed:

Aug 10, 2010

Appl. No.:

12/853953

Inventors:

Alan A. Fitzgerald - Gilbert AZ, US
Robert W. Ellis - Phoenix AZ, US
Scott Harrow - Scottsdale AZ, US

Assignee:

ADTRON, INC. - Phoenix AZ

International Classification:

G06F 12/00
G06F 12/02

US Classification:

711103, 711E12001, 711E12008

Abstract:

A flash blade and associated methods enable improved areal density of information storage, reduced power consumption, decreased cost, increased IOPS, and/or elimination of unnecessary legacy components. In various embodiments, a flash blade comprises a host blade controller, a switched fabric, and one or more storage elements configured as flash DIMMs. Storage space provided by the flash DIMMs may be presented to a user in a configurable manner. Flash DIMMs, rather than magnetic disk drives or solid state drives, are the field-replaceable unit, enabling improved customization and cost savings.