Alan E Hart

US Patent:

8320235, Nov 27, 2012

Filed:

Feb 17, 2006

Appl. No.:

11/357227

Inventors:

Erik H. Volkerink - San Jose CA, US
Alan Hart - San Carlos CA, US

Assignee:

Advantest (Singapore) Pte Ltd - Singapore

International Classification:

H04L 12/26

US Classification:

370216, 370310, 370313, 370314, 709245, 709220, 709221

Abstract:

A self-repair system provides resource failure tolerance using an interconnection network that provides interconnection information identifying connections between system resources, redundant resources and ports that are connectable to consumers of the system resources. A controller identifies both defective system resources and the affected sinks connected to the defective system resources from the interconnection network. The controller further identifies compatible resources from the system resources and redundant resources that are capable of replacing the defective system resources for each of the affected sinks from the interconnection network. The controller determines a respective cost associated with each of the compatible resources, and in response to the determined costs, selects at least one of the compatible resources as a replacement resource for each of the defective system resources. The controller further configures the interconnection network to connect the replacement resources to the affected ports instead of the defective system resources.

US Patent:

7262620, Aug 28, 2007

Filed:

Oct 31, 2005

Appl. No.:

11/264577

Inventors:

Edmundo de la Puente - Cupertino CA, US
Alan D. Hart - San Carlos CA, US

Assignee:

Verigy (Singapore) Pte. Ltd. - Singapore

International Classification:

G01R 31/26
G01R 31/02

US Classification:

324761, 324754, 324763, 3241581, 714724, 200182

Abstract:

In one embodiment, a resource matrix is provided with a first set of pins, a second set of pins, and at least one programmable switching circuit. The first set of pins electrically couples the resource matrix with a tester resource. The second set of pins electrically couples the resource matrix with a plurality of test areas. The at least one programmable switching circuit selectively couples each one of the first set of pins to different ones of the second set of pins. In one embodiment, the at least one programmable switching circuit includes a set of multiplexers. In another embodiment, the at least one programmable switching circuit includes a set of LIMMS. In another embodiment, a system is disclosed for testing a plurality of test areas with a tester resource and a resource matrix. Methods for routing signals between a tester resource and plurality of test areas are also disclosed.

US Patent:

20080252330, Oct 16, 2008

Filed:

Apr 16, 2007

Appl. No.:

11/735871

Inventors:

Alan D. Hart - San Carlos CA, US
Erik Volkerink - San Jose CA, US
Gayn Erickson - San Jose CA, US

Assignee:

Verigy Corporation - Fort Collins CO

International Classification:

G01R 31/26

US Classification:

324765

Abstract:

In accordance with one embodiment of the invention, a method of singulated die testing can be implemented. This can be implemented by obtaining a wafer and singulating the dies into individual die pieces. The singulated dies can be arranged in a separated testing arrangement and can even combine dies from multiple wafers as part of the combined arrangement. Then, testing can be implemented on the combined test arrangement.

US Patent:

20100109699, May 6, 2010

Filed:

Aug 27, 2009

Appl. No.:

12/549049

Inventors:

James C. Anderson - San Jose CA, US
Alan D. Hart - San Carlos CA, US
Kenneth D. Karklin - Pasadena CA, US

International Classification:

G01R 31/26

US Classification:

324765

Abstract:

In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.

US Patent:

20230111543, Apr 13, 2023

Filed:

Oct 8, 2021

Appl. No.:

17/497518

Inventors:

- Tokyo, JP
Ira Leventhal - San Jose CA, US
Constantinos Xanthopoulos - San Jose CA, US
Alan Hart - San Jose CA, US
Brian Buras - San Jose CA, US
Keith Schaub - San Jose CA, US

International Classification:

G01R 31/26

Abstract:

Embodiments of the present invention provide systems and methods for multidimensional parts average testing for testing devices and analyzing testing results to detect outliers according to embodiments of the present invention. The testing can include calculating multivariate (e.g., bivariate) statistics using delta measurements of like devices, a ratio of measurements, or principal component analysis that identifies eigenvectors and eigenvalues to define meta parameters, for example. Raw test result data can be converted to residual space and robust regression can be performed to prevent outlier results from influencing regression, thereby reducing overkill advantageously.