Alan James Lewandowski

US Patent:

44843089, Nov 20, 1984

Filed:

Sep 23, 1982

Appl. No.:

6/422047

Inventors:

Alan J. Lewandowski - Austin TX
Jerry D. Moench - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 104

US Classification:

364900

Abstract:

A serial data mode circuit, which provides valid data on a falling edge of a data valid signal, uses time between falling edges to prepare for the next falling edge in order to reduce the time between when a falling edge of the data valid signal occurs and when data actually becomes valid. A plurality of interconnected flip-flops selectively enable data latches containing data in response to a rising edge of the data valid signal. The data is then provided to a tri-state driver prior to the falling edge of the data valid signal. The tri-state driver is then enabled in response to the falling edge of the data valid signal.

US Patent:

47409215, Apr 26, 1988

Filed:

Oct 4, 1985

Appl. No.:

6/784450

Inventors:

Alan Lewandowski - Austin TX
Perry H. Pelley - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1134
G11C 1140

US Classification:

365189

Abstract:

A dynamic random access memory has data line pair which receives data from a selected pair of bit lines. Coupled to the data line pair is a secondary amplifier for amplifying the data provided to the data line pair from the bit line pair. The secondary amplifier has a maximum gain when the inputs are at a voltage intermediate a power supply voltage. Prior to the pair of bit lines being coupled to the data line pair, the data lines are biased to the intermediate voltage which is in the range of maximum gain of the secondary amplifier so that the secondary amplifier will operate at maximum gain which results in increased speed of operation of the dynamic random access memory.

US Patent:

46334297, Dec 30, 1986

Filed:

Dec 27, 1982

Appl. No.:

6/453008

Inventors:

Alan J. Lewandowski - Austin TX
Jerry D. Moench - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1700
G11C 1300

US Classification:

365 96

Abstract:

A technique for providing a partial memory of one half of the possible storage bits comprised of any two quadrants is implemented by decoupling the one of four decoder used for normal operation and providing a programmable decoder which is capable of being programmed to select one of any two quadrants. If only one quadrant is to form the partial memory, the programmable decoder can be programmed to select only one latch. In another embodiment, a decoder is provided which can also be programmed to select one of any three quadrants.

US Patent:

46913009, Sep 1, 1987

Filed:

Dec 20, 1985

Appl. No.:

6/811856

Inventors:

Perry H. Pelley - Austin TX
Alan Lewandowski - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1300

US Classification:

365200

Abstract:

An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redundant column access. The I/O multiplexer receives both the normal and redundant data and, in response to an input from the redundant column decoder, selects the redundant data. Column access time is improved in the case of substituted redundant columns due to the lack of inhibiting the normal column select process. Redundant columns are located physically close to the I/O multiplexer to provide for shorter I/O lines and further improved access time for the redundant columns. Floating normal bit lines are avoided in this scheme since normal column selection is not inhibited.