Alan J Martin

US Patent:

6447309, Sep 10, 2002

Filed:

Dec 12, 2000

Appl. No.:

09/735116

Inventors:

Han Y. Ko - Milpitas CA
Robert C. Cyphers - Fremont CA
Tomonori Hirai - Sunnyvale CA
Keith Y. Oka - Los Altos CA
Alan D. Martin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H02H 720

US Classification:

439106

Abstract:

An apparatus for suppressing power bus bouncing in a hot-swappable system has been developed. The apparatus includes a connection module with three interior pins for: the power return; the power supply; and the system ground. The system ground pin is shorter than the other two so that it makes contact with the power bus after the bouncing from the return and supply pins has subsided.

US Patent:

20140002046, Jan 2, 2014

Filed:

Jun 28, 2013

Appl. No.:

13/930504

Inventors:

Alan Dean Martin - San Jose CA, US

International Classification:

H02M 3/156

US Classification:

323282

Abstract:

The disclosed methodology for buck-boost inverted voltage conversion uses a boost stage coupled to a charge pump stage at a switch node controlled by a transistor switch coupled between the switch node and ground. The boost stage includes a boost inductor coupled between an input supply voltage and the switch node, and the charge pump stage includes a charge pump capacitor coupled between the switch node and a pump node which is coupled to the load and an output capacitor in parallel with the load. The regulated inverted output voltage is supplied to the output capacitor and the load by: (a) in a first phase, switching the transistor switch to conducting to couple the switch node to ground, and thereby (i) transferring energy from a source of input voltage source to the boost inductor, and (ii) transferring energy from a charge pump capacitor to the output node, and (b) in the second phase, switching the transistor switch to non-conducting and clamping the charge pump capacitor at a positive reference voltage, and thereby transferring energy from the boost inductor to the charge pump capacitor. In one embodiment, the positive reference voltage is the input voltage (i.e., during the second phase, the charge pump capacitor is clamped to the input voltage).

US Patent:

20150362705, Dec 17, 2015

Filed:

Jun 17, 2014

Appl. No.:

14/307255

Inventors:

- Santa Clara CA, US
Alan MARTIN - San Jose CA, US

International Classification:

G02B 13/00
B29C 33/00

Abstract:

Wafer-level optical elements and the concave spacer-wafer apertures in which they are formed are disclosed. The wafer-level optical elements include a spacer wafer comprising a plurality of apertures. Each aperture has a concave shape in a planar cross-section of the spacer wafer and an overflow region intersecting the planar cross-section. The wafer-level optical elements also include an array of optical elements, each optical element of the array being formed of cured flowable material within a respective one of the plurality of apertures. A portion of the cured flowable material forming each optical element extends into the overflow region of the respective aperture of the plurality of apertures. The spacer wafer includes a plurality of apertures, each of the plurality of apertures having a concave shape in a planar cross-section of the spacer wafer. Each of the plurality of apertures includes an overflow region intersecting the planar cross-section.

US Patent:

20150318325, Nov 5, 2015

Filed:

May 5, 2014

Appl. No.:

14/270281

Inventors:

- Santa Clara CA, US
Yi Quin - Shanghai, CN
Ward Zhang - Shanghai, CN
Alan Martin - San Jose CA, US

Assignee:

OmniVision Technologies, Inc. - Santa Clara CA

International Classification:

H01L 27/146

Abstract:

A method for black coating camera cubes at wafer level includes expanding the gap between individual diced camera cubes of the wafer by stretching tape securing the diced camera cubes. The method includes applying a black coating layer to the stretched camera cubes, laser trimming undesired portions of the black coating layer, and removing the undesired portions of the black coating layer.