Alan Mark Morton

US Patent:

59599260, Sep 28, 1999

Filed:

Apr 13, 1998

Appl. No.:

9/059244

Inventors:

Brian W. Jones - Richardson TX
Alan Mark Morton - Dallas TX

Assignee:

Dallas Semiconductor Corp. - Dallas TX

International Classification:

G11C 700

US Classification:

365226

Abstract:

A programmable power controller controls power between a primary power source and a secondary power source and powering first circuitry. The primary power source has a first voltage and the secondary power source has a second voltage. A control register has a first field, which is field used to activate circuitry used to direct power from the primary power source to the secondary power source. First logic circuitry compares the first voltage and the second voltage to determine which is greater and then couples the primary power source or the secondary power source, depending upon which is greater, to power the first logic circuitry, second logic circuitry, and memory. The memory is coupled to the first logic circuitry and is read and written to via an input/output buffer. The second logic circuitry is coupled to the memory and to said first logic circuitry and activates write protection circuitry to prevent writing to the memory if the secondary power source is powering the first logic circuitry, the second logic circuitry, and the memory. A multiple voltage interface system comprises a first voltage interface able to be electrically coupled to first power supply having a first voltage level, a second voltage interface able to be electrically coupled to a second power supply having a second voltage level and switching circuitry to switch said second voltage interface on to receive and adjust said second voltage level to power an application system or to switch said first voltage interface on to receive and adjust said first voltage level to power said application system.

US Patent:

55373607, Jul 16, 1996

Filed:

Sep 16, 1994

Appl. No.:

8/308462

Inventors:

Brian W. Jones - Richardson TX
Alan M. Morton - Dallas TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

G11C 700

US Classification:

365226

Abstract:

A programmable power controller controls power between a primary power source and a secondary power source and powering first circuitry. The primary power source has a first voltage and the secondary power source has a second voltage. A control register has a first field, which is field used to activate circuitry used to direct power from the primary power source to the secondary power source. First logic circuitry compares the first voltage and the second voltage to determine which is greater and then couples the primary power source or the secondary power source, depending upon which is greater, to power the first logic circuitry, second logic circuitry, and memory. The memory is coupled to the first logic circuitry and is read and written to via an input/output buffer. The second logic circuitry is coupled to the memory and to said first logic circuitry and activates write protection circuitry to prevent writing to the memory if the secondary power source is powering the first logic circuitry, the second logic circuitry, and the memory.

US Patent:

55679935, Oct 22, 1996

Filed:

Jun 23, 1994

Appl. No.:

8/264389

Inventors:

Brian W. Jones - Richardson TX
Alan M. Morton - Dallas TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H02J 314

US Classification:

307 43

Abstract:

A programmable power controller for controlling power between a primary power source and a second power source and powering first circuitry, each of which has a voltage, comprises a control register having a first field, which is used to activate circuitry used to direct power from the primary power source to the second power source, and circuitry to compare the first voltage and the second voltage to determine which is greater and then coupling the primary power source or the second power source depending upon which is greater to power the first circuitry. The control register also has a second field used to select an electrical path having a first voltage drop that ensures the primary power source will have a higher voltage when the primary power source is active under normal operating conditions and a third field used to select an electrical path of a plurality of electrical paths, each electrical path having a variety of voltage drops and resistances. The second power source is preferably chargeable, such as a capacitor or a rechargeable battery.

US Patent:

20220329212, Oct 13, 2022

Filed:

Jun 16, 2021

Appl. No.:

17/348982

Inventors:

- Edinburgh, GB
Xin Zhao - Austin TX, US
Jing Bai - Austin TX, US
John L. Melanson - Austin TX, US
Ku He - Austin TX, US
Wai-Shun Shum - Austin TX, US
Xiaofan Fei - Austin TX, US
Alan M. Morton - Austin TX, US

International Classification:

H03F 1/32
H04R 3/02
H04R 29/00
H03F 3/183

Abstract:

An amplification system with an output driver stage for providing an output signal to acoustic output transducers such as speakers or haptic output devices removes signal distortion caused by output stage non-linearities by pre-distorting an input signal. The system includes the output driver stage, an input stage for receiving the input signal, and a processing block that receives the input signal and provides an output signal to the output driver stage. The processing block includes a pre-distortion circuit that applies a pre-distortion function to the input signal to generate the output signal if a signal level of the input signal is greater than a threshold amplitude, and if the signal level is less than or equal to the threshold amplitude, generates the output signal from the input signal by bypassing the pre-distortion circuit.

US Patent:

20190115886, Apr 18, 2019

Filed:

Sep 17, 2018

Appl. No.:

16/133045

Inventors:

- Edinburgh, GB
Alan Mark MORTON - Austin TX, US
Xin ZHAO - Austin TX, US
Lei ZHU - Austin TX, US
Xiaofan FEI - Austin TX, US
Johann G. GABORIAU - Austin TX, US
John L. MELANSON - Austin TX, US
Amar VELLANKI - Cedar Park TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H03G 3/30
H03F 3/187
H04R 3/00

Abstract:

A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

US Patent:

20190115909, Apr 18, 2019

Filed:

Dec 13, 2018

Appl. No.:

16/219187

Inventors:

- Edinburgh, GB
Alan Mark MORTON - Austin TX, US
Xin ZHAO - Austin TX, US
Lei ZHU - Austin TX, US
Xiaofan FEI - Austin TX, US
Johann G. GABORIAU - Austin TX, US
John L. MELANSON - Austin TX, US
Amar VELLANKI - Cedar Park TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H03K 7/08
H02M 3/157
G06F 1/025

Abstract:

A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

US Patent:

20180159488, Jun 7, 2018

Filed:

Jan 31, 2018

Appl. No.:

15/884912

Inventors:

- Edinburgh, GB
Tejasvi DAS - Austin TX, US
Xiaofan FEI - Austin TX, US
Alan Mark MORTON - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H03F 3/217
H03F 3/187
H03F 1/34
H03F 3/38

Abstract:

An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.

US Patent:

20180091102, Mar 29, 2018

Filed:

Sep 27, 2016

Appl. No.:

15/277465

Inventors:

- Edinburgh, GB
Tejasvi DAS - Austin TX, US
Xiaofan FEI - Austin TX, US
Alan Mark MORTON - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H03F 3/217
H03F 3/187
H03F 1/34

Abstract:

An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.