Alan W Thomas

US Patent:

6842222, Jan 11, 2005

Filed:

Apr 4, 2003

Appl. No.:

10/406888

Inventors:

Gerhard Kunkel - Radebeul, DE
Shahid Butt - Ossining NY, US
Alan Thomas - Hughsonville NY, US
Juergen Preuninger - Munich, DE

Assignee:

Infineon Technologies AG

International Classification:

G03B 2742
G03B 2732

US Classification:

355 53, 355 77, 430311

Abstract:

A projected image is formed during a material substrate. A photolithographic mask is illuminated with substantially coherent light at an oblique angle of incidence with respect to a surface of the photolithographic mask. The photolithographic mask includes a substantially transparent mask substrate and one or more lines and spaces patterns formed on the mask substrate and having a periodicity P. The mask substrate includes at least one phase shifting region. At least part of the light that is transmitted through the photolithographic mask is collected using one or more projection lenses which project the portion of the transmitted light onto the material substrate. The material substrate is disposed substantially parallel with, but at a distance from, a focal plane of the projection lens system. The phase shifting region of the mask substrate and the distance from the focal plane are selected such that a substantially focused image is projected onto the material substrate that includes the lines and spaces patterned but with a periodicity P/2.

US Patent:

20050158116, Jul 21, 2005

Filed:

Apr 3, 2003

Appl. No.:

10/509555

Inventors:

Carol Belansky - Montvale NJ, US
Ian Corkhill - Wayne NJ, US
Carl Dibnah - Hull, GB
Michael Love - Montvale NJ, US
Lamson Nguyen - Wayne NJ, US
Diane Neiman - Colonia NJ, US
Leonard Spitzer - Montvale NJ, US
John Studer - Morris Plains NJ, US
Alan Thomas - Wayne NJ, US
Jeanne Weller - Montvale NJ, US
Lino Ferri - Middletown NJ, US
Charles Ashley - Clinton NJ, US
Tor Alden - Gadstone NJ, US

International Classification:

A46B005/02
A46B011/04

US Classification:

401270000, 401190000

Abstract:

A combination cleaning device useful in the cleaning of hard surfaces, or soft surfaces which combination cleaning device includes a cleaning means particularly an abrasive cleaning means such as a brush, abrasive pad or other physical means which is used to contact a surface requiring cleaning and/or disinfecting treatment, and which combination cleaning device further includes a chemical cleaning composition which may optionally also provide a sanitizing benefit, which combination cleaning device is manually graspable by a consumer. In preferred embodiments the chemical cleaning composition is provided in a pressurized or pressurizable vessel which is at least partially enclosed within the said combination cleaning device whererin the user of the device dispenses the cleaning composition which is expelled from the vessel and then to the cleaning means. Methods relating to the use of the device as well as methods or manufacturing the device are also disclosed.

US Patent:

D3972623, Aug 25, 1998

Filed:

Mar 29, 1996

Appl. No.:

D/577852

Inventors:

Alan Thomas - Roosevelt NY

International Classification:

0604

US Classification:

D 6446

US Patent:

20200075428, Mar 5, 2020

Filed:

Aug 30, 2018

Appl. No.:

16/117258

Inventors:

- Armonk NY, US
Ravikumar RAMACHANDRAN - Pleasantville NY, US
Albert CHU - Nashua NH, US
Alan THOMAS - Hopewell Junction NY, US
Kafai LAI - Poughkeepsie NY, US

International Classification:

H01L 21/8238

Abstract:

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.