Albert L Mclaughlin

US Patent:

41595327, Jun 26, 1979

Filed:

Aug 4, 1977

Appl. No.:

5/821931

Inventors:

Edward F. Getson - Lynn MA
John H. Kelley - Nashua NH
Albert T. McLaughlin - Hudson NH
Donald J. Rathbun - Andover MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364900

Abstract:

A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device. The input register to the predictor FIFO thereupon is emptied, and another data request may be made to main memory.

US Patent:

47776196, Oct 11, 1988

Filed:

Mar 30, 1987

Appl. No.:

7/032422

Inventors:

Thomas J. Fitzgerald - Cambridge MA
Albert T. McLaughlin - Hudson NH

Assignee:

Honeywell Bull, Inc. - Minneapolis MN

International Classification:

G06F 1100
G01R 3128

US Classification:

364900

Abstract:

A method and apparatus for determining if matching units of an electronic system or a subsystem are assembled includes a single scratchpad memory which is addressed by the units on alternate cycles. A microprogram stored in one unit operates in synchronism with a microprogram in the other unit to write into and to test the contents of a location in scratchpad memory to determine if the two units would be operational with each other during normal operation.

US Patent:

41617789, Jul 17, 1979

Filed:

Jul 19, 1977

Appl. No.:

5/816985

Inventors:

Edward F. Getson - Lynn MA
John H. Kelley - Nashua NH
Donald J. Rathbun - Andover MA
Albert T. McLaughlin - Hudson NH

Assignee:

Honeywell Information Systems, Inc. - Waltham MA

International Classification:

G06F 306

US Classification:

364200

Abstract:

In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory.