Aleksandar Kavcic

US Patent:

6438180, Aug 20, 2002

Filed:

Mar 1, 1999

Appl. No.:

09/259195

Inventors:

Aleksandar Kavcic - Cambridge MA
Jose M. F. Moura - Pittsburgh PA

Assignee:

Carnegie Mellon University - Pittsburgh PA

International Classification:

H03D 100

US Classification:

375341, 714796

Abstract:

A method of determining branch metric values in a detector. The method includes receiving a plurality of time variant signal samples, the signal samples having one of signal-dependent noise, correlated noise, and both signal dependent and correlated noise associated therewith. The method also includes selecting a branch metric function at a certain time index and applying the selected function to the signal samples to determine the metric values.

US Patent:

20040066863, Apr 8, 2004

Filed:

Oct 8, 2002

Appl. No.:

10/266241

Inventors:

Wei Zeng - Cambridge MA, US
Aleksandar Kavcic - Cambridge MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H03D001/00

US Classification:

375/340000

Abstract:

A method for detecting data symbols corrupted by intersymbol interference and timing error, comprises calculating a first plurality of state probabilities for received symbols using a forward recursive process on a joint intersymbol interference/timing error (ISI/TE) trellis, calculating a second plurality of state probabilities for the received symbols using a backward recursive process on the joint ISI/TE trellis, and using the first plurality of state probabilities and the second plurality of state probabilities to calculate a posteriori state transition probabilities for the received symbols. An apparatus that performs the method is also disclosed.

US Patent:

20050193320, Sep 1, 2005

Filed:

Feb 9, 2004

Appl. No.:

10/774763

Inventors:

Nedeljko Varnica - Cambridge MA, US
Aleksandar Kavcic - Cambridge MA, US
Marc Fossorier - Honolulu HI, US

Assignee:

President and Fellows of Harvard College - Cambridge MA
University of Hawaii - Honolulu HI

International Classification:

H03M013/00
G06F011/00

US Classification:

714800000

Abstract:

Various modifications to conventional information coding schemes that result in an improvement in one or more performance measures for a given coding scheme. Some examples are directed to improved decoding techniques for linear block codes, such as low-density parity-check (LDPC) codes. In one example, modifications to a conventional belief-propagation (BP) decoding algorithm for LDPC codes significantly improve the performance of the decoding algorithm so as to more closely approximate that of the theoretically optimal maximum-likelihood (ML) decoding scheme. BP decoder performance generally is improved for lower code block lengths, and significant error floor reduction or elimination may be achieved for higher code block lengths. In one aspect, significantly improved performance of a modified BP algorithm is achieved while at the same time essentially maintaining the benefits of relative computational simplicity and execution speed of a conventional BP algorithm as compared to an ML decoding scheme. In another aspect, modifications for improving the performance of conventional BP decoders are universally applicable to “off the shelf” LDPC encoder/decoder pairs. Furthermore, the concepts underlying the various methods and apparatus disclosed herein may be more generally applied to various decoding schemes involving iterative decoding algorithms and message-passing on graphs, as well as coding schemes other than LDPC codes to similarly improve their performance. Exemplary applications for improved coding schemes include wireless (mobile) networks, satellite communication systems, optical communication systems, and data recording and storage systems (e.g., CDs, DVDs, hard drives, etc.).

US Patent:

20080123210, May 29, 2008

Filed:

Nov 6, 2006

Appl. No.:

11/593856

Inventors:

Wei Zeng - San Diego CA, US
Lan Lan - Davis CA, US
Yuan X. Lee - San Jose CA, US
Aleksandar Kavcic - Cambridge MA, US

International Classification:

G11B 5/09

US Classification:

360 51

Abstract:

Embodiments of the present invention pertain to handling synchronization errors potentially experienced by a storage device. According to one embodiment, a system for handling synchronization errors potentially experienced by a storage device includes a joint detector and a decoder. The joint detector detects transmitted data. The joint detector also detects timing errors that potentially result from the transmission of the data. The joint detector communicates information about the transmitted data and the timing errors with the decoder iteratively in a loop to reduce the amount of the transmitted data that is lost.

US Patent:

20140223260, Aug 7, 2014

Filed:

Jan 17, 2014

Appl. No.:

14/157730

Inventors:

- Honolulu HI, US
Xiujie Huang - Guangzhou, CN
Aleksandar Kavcic - Honolulu HI, US

International Classification:

H03M 13/11
G06F 11/10

US Classification:

714763

Abstract:

A method for determining decision metrics in a detector for a memory device. The method includes receiving a plurality of signal samples and extracting a set of statistics from the signal samples, wherein at least one of the statistics is non-linear or complex, is derived from a plurality of the signal samples, and is not a function of at least one real linear statistic that is derived from a plurality of the signal samples. The method also includes applying at least one decision metric function to the set of statistics to determine at least one decision metric value corresponding to at least one postulated symbol.