Alex K Mak

US Patent:

7616499, Nov 10, 2009

Filed:

Dec 28, 2006

Appl. No.:

11/617541

Inventors:

Jun Wan - Sunnyvale CA, US
Jeffrey W. Lutze - San Jose CA, US
Jian Chen - San Jose CA, US
Yan Li - Milpitas CA, US
Alex Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34
G11C 16/04
G11C 16/06

US Classification:

36518522, 36518503, 36518524

Abstract:

Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.

US Patent:

7652918, Jan 26, 2010

Filed:

Dec 28, 2006

Appl. No.:

11/617546

Inventors:

Jun Wan - Sunnyvale CA, US
Jeffrey W. Lutze - San Jose CA, US
Jian Chen - San Jose CA, US
Yan Li - Milpitas CA, US
Alex Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34
G11C 16/04

US Classification:

36518503, 36518522, 36518518

Abstract:

A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.

US Patent:

7715255, May 11, 2010

Filed:

Jun 14, 2007

Appl. No.:

11/763287

Inventors:

Loc Tu - San Jose CA, US
Jian Chen - San Jose CA, US
Alex Mak - Los Altos Hills CA, US
Tien-Chien Kuo - Sunnyvale CA, US
Long Pham - San Ramon CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 7/00

US Classification:

365195, 36518504, 36523003

Abstract:

Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

US Patent:

8473809, Jun 25, 2013

Filed:

Jul 19, 2010

Appl. No.:

12/839237

Inventors:

Jun Wan - San Jose CA, US
Alex Mak - Los Altos Hills CA, US
Tien-Chien Kuo - Sunnyvale CA, US
Yan Li - Milpitas CA, US
Jian Chen - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G06F 11/00
G11C 29/00
G11C 7/00

US Classification:

714763, 714703, 714718, 365200, 365201, 365204

Abstract:

Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.

US Patent:

20080310242, Dec 18, 2008

Filed:

Jun 14, 2007

Appl. No.:

11/763292

Inventors:

Loc Tu - San Jose CA, US
Jian Chen - San Jose CA, US
Alex Mak - Los Altos Hills CA, US
Tien-chien Kuo - Sunnyvale CA, US
Long Pham - San Ramon CA, US

International Classification:

G11C 7/00
G11C 8/00

US Classification:

365200, 36523001

Abstract:

Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

US Patent:

20130070530, Mar 21, 2013

Filed:

Sep 18, 2012

Appl. No.:

13/622045

Inventors:

Jian Chen - San Jose CA, US
Sergei Gorobets - Edinburgh, GB
Steven Sprouse - San Jose CA, US
Tien-Chien Kuo - Sunnyvale CA, US
Yan Li - Milpitas CA, US
Seungpil Lee - San Ramon CA, US
Alex Mak - Los Altos CA, US
Deepanshu Dutta - Santa Clara CA, US
Masaaki Higashitani - Cupertino CA, US

Assignee:

SANDISK TECHNOLOGIES INC. - Plano TX

International Classification:

G11C 16/04

US Classification:

36518511, 36518519, 36518517, 36518518

Abstract:

A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

US Patent:

20130107628, May 2, 2013

Filed:

Nov 2, 2011

Appl. No.:

13/287343

Inventors:

Yingda Dong - San Jose CA, US
Alex Mak - Los Altos Hills CA, US
Seungpil Lee - San Ramon CA, US
Johann Alsmeier - San Jose CA, US

International Classification:

G11C 16/16

US Classification:

36518517

Abstract:

An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

US Patent:

20150063033, Mar 5, 2015

Filed:

Nov 10, 2014

Appl. No.:

14/536923

Inventors:

- Plano TX, US
Alex Mak - Los Altos Hills CA, US
Seungpil Lee - San Ramon CA, US
Johann Alsmeier - San Jose CA, US

Assignee:

SANDISK TECHNOLOGIES INC. - Plano TX

International Classification:

G11C 16/14
G11C 16/04

US Classification:

36518517

Abstract:

An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.