Alexander Davis Elliott

US Patent:

6870243, Mar 22, 2005

Filed:

Nov 27, 2002

Appl. No.:

10/306834

Inventors:

Alexander James Elliott - Tempe AZ, US
Jeffrey Dale Crowder - Phoenix AZ, US
Monte Gene Miller - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L029/40
H01L023/48
H01L023/495
H01L027/095

US Classification:

257666, 257669, 257675, 257762, 257782, 257473, 257763, 257784, 257786, 257758, 257700, 257701

Abstract:

A thin GaAs Substrate can be provided with a copper back-metal layer to allow the GaAs Substrate to be packaged using conventional plastic packaging technologies. By providing the GaAs Substrate with a copper back-metal layer, the GaAs Substrate can be made thinner than 2 mils (about 50 microns), thereby reducing heat dissipation problems and allowing the semiconductor die to be compatible with soft-solder technologies. By enabling the semiconductor die to be packaged in a plastic package substantial cost savings can be achieved.

US Patent:

6982483, Jan 3, 2006

Filed:

May 30, 2003

Appl. No.:

10/448548

Inventors:

Robert J. McLaughlin - Phoenix AZ, US
Alexander J. Elliott - Tempe AZ, US
Mall Mahalingam - Scottsdale AZ, US
Scott D. Marshall - Chandler AZ, US
Pierre-Marie J. Piel - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/34

US Classification:

257728, 257701

Abstract:

The disclosures made herein relate to RF power semiconductor devices. In accordance with one embodiment of the disclosures made herein, a RF power plastic semiconductor device comprises a semiconductor (RF) device, a Low Temperature Co-Fired Ceramic (LTCC) impedance matching structure electrically connected to the RF device and a plastic package body formed over the RF device and the impedance matching structure. The LTCC impedance matching structure comprises a metallized layer overlying a major body portion of the impedance matching structure and comprises a passivation layer on the metallized layer. The passivation layer enhances bond strength of a mold compound of the plastic package body to the metallized layer. Portions of the metallized layer are exposed through the passivation layer for enabling electrical interconnects to be formed between the LTCC impedance matching structure and the RF device. Preferably, RF power plastic packages in accordance with embodiments of the disclosures made herein exhibit terminal impedance of at least about twice that of conventional RF power plastic packages.

US Patent:

6996897, Feb 14, 2006

Filed:

Jul 31, 2002

Appl. No.:

10/208867

Inventors:

Alexander J. Elliott - Tempe AZ, US
William M. Strom - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

B23P 15/00

US Classification:

29827, 29825, 438123, 257685

Abstract:

method for making a mount for at least two electronic devices forming a first mounting surface () from a material (), and forming a second mounting surface () from the material (). The first mounting surface () is connected to, but spaced from, the second mounting surface () by a mounting surface distance (). The method further comprises reducing the mounting surface distance ().

US Patent:

7091602, Aug 15, 2006

Filed:

Dec 13, 2002

Appl. No.:

10/318699

Inventors:

Alexander J. Elliott - Tempe AZ, US
L. Mali Mahalingam - Scottsdale AZ, US
William M. Strom - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/10
H01L 23/34

US Classification:

257706, 257625

Abstract:

A system of mold locks () is formed on a heatsink () of a packaged semiconductor to prevent/mitigate delamination. The mold locks () anchor a plastic mold compound () that forms the protective cover for the packaged semiconductor die. The mold locks () are miniaturized to allow the positioning of them within the flag portion of the heatsink () and leadframe () such that a semiconductor die can be anchored above the mold locks () formed within the flag portion of the heatsink/lead frame (). The miniaturized size of the said moldlocks ( do not detract from the purpose of the die attach solder ().

US Patent:

7092890, Aug 15, 2006

Filed:

Feb 3, 2005

Appl. No.:

11/050079

Inventors:

Alexander J. Elliott - Tempe AZ, US
Jeffrey D. Crowder - Phoenix AZ, US
Monte G. Miller - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G21K 1/12

US Classification:

705 1, 257666, 257473, 257669, 257675, 257700

Abstract:

A thin GaAs Substrate can be provided with a copper back-metal layer to allow the GaAs Substrate to be packaged using conventional plastic packaging technologies. By providing the GaAs Substrate with a copper back-metal layer, the GaAs Substrate can be made thinner than 2 mils (about 50 microns), thereby reducing heat dissipation problems and allowing the semiconductor die to be compatible with soft-solder technologies. By enabling the semiconductor die to be packaged in a plastic package substantial cost savings can be achieved.

US Patent:

7445967, Nov 4, 2008

Filed:

Jan 20, 2006

Appl. No.:

11/336368

Inventors:

David F. Abdo - Scottsdale AZ, US
Alexander J. Elliott - Tempe AZ, US
Lakshminarayan Viswanathan - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44

US Classification:

438123

Abstract:

A method of packaging a semiconductor die includes the steps of providing a flange (), coupling one or more active die () to the flange with a lead-free die attach material (), staking a leadframe () to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (), and applying a plastic material () over the flange, the one or more active die, the leadframe, and the interconnect structure.

US Patent:

8310042, Nov 13, 2012

Filed:

Jun 14, 2006

Appl. No.:

11/424183

Inventors:

Alexander J. Elliott - Tempe AZ, US
L. M. Mahalingam - Scottsdale AZ, US
William M. Strom - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/10
H01L 23/34

US Classification:

257706, 257E23092

Abstract:

A system of mold locks () is formed on a heatsink () of a packaged semiconductor to prevent/mitigate delamination. The mold locks () anchor a plastic mold compound () that forms the protective cover for the packaged semiconductor die. The mold locks () are miniaturized to allow the positioning of them within the flag portion of the heatsink () and leadframe () such that a semiconductor die can be anchored above the mold locks () formed within the flag portion of the heatsink/lead frame (). The miniaturized size of the said moldlocks ( do not detract from the purpose of the die attach solder ().

US Patent:

20090023248, Jan 22, 2009

Filed:

Sep 30, 2008

Appl. No.:

12/242622

Inventors:

David F. Abdo - Scottsdale AZ, US
Alexander J. Elliott - Tempe AZ, US
Lakshminarayan Viswanathan - Phoenix AZ, US

International Classification:

H01L 21/56
H01L 23/495

US Classification:

438112, 257666, 257E21502, 257E23031

Abstract:

A method of packaging a semiconductor die includes the steps of providing a flange (), coupling one or more active die () to the flange with a lead-free die attach material (), staking a leadframe () to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (), and applying a plastic material () over the flange, the one or more active die, the leadframe, and the interconnect structure.