Alexander W Schaefer

US Patent:

7925937, Apr 12, 2011

Filed:

Jan 7, 2008

Appl. No.:

11/970018

Inventors:

Joel T. Irby - Austin TX, US
Grady L. Giles - Dripping Springs TX, US
Alexander W. Schaefer - Austin TX, US
Gregory A. Constant - Austin TX, US
Floyd L. Dankert - Austin TX, US
Amy M. Novak - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714718, 714726

Abstract:

An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.

US Patent:

7355881, Apr 8, 2008

Filed:

Nov 22, 2005

Appl. No.:

11/285670

Inventors:

Floyd L. Dankert - Austin TX, US
Victor F. Andrade - Austin TX, US
Randal L. Posey - Austin TX, US
Michael K. Ciraula - Round Rock TX, US
Alexander W. Schaefer - Austin TX, US
Jerry D. Moench - Austin TX, US
Soolin Kao Chrudimsky - Austin TX, US
Michael C. Braganza - Austin TX, US
Jan Michael Huber - Austin TX, US
Amy M. Novak - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 11/00
G11C 7/10
G11C 7/00

US Classification:

365156, 365154, 36518902, 365202

Abstract:

A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

US Patent:

20180226968, Aug 9, 2018

Filed:

Apr 20, 2017

Appl. No.:

15/492249

Inventors:

- Sunnyvale CA, US
Alexander W. Schaefer - Austin TX, US

International Classification:

H03K 19/00
H03K 19/20

Abstract:

A dynamic logic circuit includes a pull-up network coupled between a voltage supply and a dynamic node and receives a first input signal and a second input signal. A pull-down network is coupled between the dynamic node and a ground node and receives the first input signal and the second input signal. A pre-charge network is in parallel with the pull-up or pull-down network and pre-charges the dynamic node to a high or low voltage level prior to evaluation of the first and second input signals. The transistors in the pull-up network are substantially different in size than the transistors in the pull-down network.