Aliasgar S Madraswala

US Patent:

20090080248, Mar 26, 2009

Filed:

Sep 25, 2007

Appl. No.:

11/861240

Inventors:

Rezaul Haque - Folsom CA, US
Darshak A. Udeshi - Folsom CA, US
Karthi Ramamurthi - Folsom CA, US
Nathan C. Chrisman - Rescue CA, US
Aliasgar S. Madraswala - Folsom CA, US
Kevin P. Flanagan - Rancho Cordova CA, US

International Classification:

G11C 16/34
H04B 1/38

US Classification:

36518503, 36518522, 455 902

Abstract:

A wireless device that includes a memory device having an engine to execute a voting algorithm to average a memory cell data sensing result over time to provide a charge placement in the memory cell.

US Patent:

20220415380, Dec 29, 2022

Filed:

Jun 24, 2021

Appl. No.:

17/357466

Inventors:

- Santa Clara CA, US
Aliasgar S. Madraswala - Folsom CA, US
Bharat Pathak - Folsom CA, US
Binh Ngo - Folsom CA, US
Netra Mahuli - Folsom CA, US
Ahsanur Rahman - Santa Clara CA, US

International Classification:

G11C 11/4076
G11C 11/408
G11C 11/4094
G11C 11/4096

Abstract:

Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

US Patent:

20220262431, Aug 18, 2022

Filed:

May 5, 2022

Appl. No.:

17/737461

Inventors:

- Santa Clara CA, US
Aliasgar S. Madraswala - Folsom CA, US
John Egler - Folsom CA, US

International Classification:

G11C 11/56
G11C 16/04
G11C 16/10
G11C 16/26

Abstract:

Systems, apparatuses, and methods provide for technology for distinguishing an erased state, a first pass programmed state, and a second pass programmed state of a memory page. A threshold voltage state verify sense is performed. A memory page status is determined based on the threshold voltage state verify sense. The memory page status is one of erased, programmed with first pass data, and programmed with second pass data based on the threshold voltage state verify sense. A program continuation is performed after a program interruption based on the memory page status.

US Patent:

20230086751, Mar 23, 2023

Filed:

Sep 23, 2021

Appl. No.:

17/483279

Inventors:

- Santa Clara CA, US
Aliasgar Madraswala - Folsom CA, US
Pranav Chava - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 16/10
G11C 16/16
G11C 16/28
G11C 16/30
G11C 16/08

Abstract:

Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.

US Patent:

20230061293, Mar 2, 2023

Filed:

Aug 25, 2021

Appl. No.:

17/411919

Inventors:

- Santa Clara CA, US
Archana Tankasala - Santa Clara CA, US
Aliasgar S. Madraswala - Folsom CA, US
Shantanu Rajwade - Santa Clara CA, US

International Classification:

G11C 16/34
G11C 16/10
G11C 16/26
G11C 16/30
G11C 16/08
G11C 16/24

Abstract:

Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.

US Patent:

20230062668, Mar 2, 2023

Filed:

Aug 25, 2021

Appl. No.:

17/411899

Inventors:

- Santa Clara CA, US
Aliasgar Madraswala - Folsom CA, US
Sandeep Rasoori - Folsom CA, US
Trupti Bemalkhedkar - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.

US Patent:

20210383880, Dec 9, 2021

Filed:

Jun 8, 2020

Appl. No.:

16/895890

Inventors:

- Santa Clara CA, US
Aliasgar S. MADRASWALA - Folsom CA, US
Sagar UPADHYAY - Folsom CA, US
Bhaskar VENKATARAMAIAH - Folsom CA, US

International Classification:

G11C 16/34
G11C 16/10
G11C 16/26
G11C 16/30
G11C 16/08
G11C 7/22

Abstract:

For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

US Patent:

20210151098, May 20, 2021

Filed:

Dec 23, 2020

Appl. No.:

17/133459

Inventors:

- Santa Clara CA, US
Suresh NAGARAJAN - Folsom CA, US
Aliasgar S. MADRASWALA - Folsom CA, US
Yihua ZHANG - Cupertino CA, US

International Classification:

G11C 11/56
G11C 7/10
G11C 29/42

Abstract:

Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.