Alison V Davis

US Patent:

20070218685, Sep 20, 2007

Filed:

Mar 17, 2006

Appl. No.:

11/384143

Inventors:

Swaminathan Sivakumar - Portland OR, US
Charles Wallace - Portland OR, US
Alison Davis - Hillsboro OR, US
Nadia Rahhal-Orabi - Hillsboro OR, US

International Classification:

H01L 21/44

US Classification:

438675000, 257E21585

Abstract:

A method to form transistor contacts begins with providing a transistor that includes a gate stack and first and second diffusion regions formed on a substrate, and a dielectric layer formed atop the gate stack and the diffusion regions. A first photolithography process forms first and second diffusion trench openings for the first and second diffusion regions. A sacrificial layer is then deposited into the first and second diffusion trench openings. Next, a second photolithography process forms a gate stack trench opening for the gate stack and a local interconnect trench opening coupling the gate stack trench opening to the first diffusion trench opening. The second photolithography process is carried out independent of the first photolithography process. The sacrificial layer is then removed and a metallization process is carried out to fill the first and second diffusion trench openings, the gate stack trench opening, and the local interconnect trench opening with a metal layer.

US Patent:

20090001431, Jan 1, 2009

Filed:

Jun 26, 2007

Appl. No.:

11/821971

Inventors:

Nadia Rahhal-Orabi - Hillsboro OR, US
Charles H. Wallace - Portland OR, US
Alison Davis - Hillsboro OR, US
Swaminathan Sivakumar - Portland OR, US

International Classification:

H01L 29/78
H01L 21/4763

US Classification:

257288, 438618, 257E29255, 257E21495

Abstract:

In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

US Patent:

20100171156, Jul 8, 2010

Filed:

Mar 15, 2010

Appl. No.:

12/723768

Inventors:

Nadia Rahhal-Orabi - Hillboro OR, US
Charles H. Wallace - Portland OR, US
Alison Davis - Hillsboro OR, US
Swaminathan Sivakumar - Portland OR, US

International Classification:

H01L 23/48
H01L 21/768
H01L 21/336
H01L 29/78

US Classification:

257288, 438142, 438637, 257E21576, 257E21409, 257E23011, 257E29255

Abstract:

In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

US Patent:

20220392898, Dec 8, 2022

Filed:

Jun 7, 2021

Appl. No.:

17/340429

Inventors:

- Santa Clara CA, US
Mohit K. HARAN - Hillsboro OR, US
Mohammad HASAN - Aloha OR, US
Biswajeet GUHA - Hillsboro OR, US
Alison V. DAVIS - Portland OR, US
Leonard P. GULER - Hillsboro OR, US

International Classification:

H01L 27/092
H01L 29/78
H01L 29/06
H01L 29/66

Abstract:

Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.