Allan C Ward

US Patent:

6476957, Nov 5, 2002

Filed:

Jul 17, 2000

Appl. No.:

09/620324

Inventors:

Allan Ward - Alexandria VA
Keith J. Williams - Accokeek MD
Paul D. Biernacki - Alexandria VA
Lee T. Nichols - Springfield VA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

G02F 135

US Classification:

359326, 333167, 333176

Abstract:

An image rejecting microwave photonic downconverter uses a microwave sub-carrier modulation technique without concern for image frequency interference in the shifted signal, thereby allowing telecommunications systems to downconvert densely multiplexed communications channels into a low frequency band where conventionqal electronics can perform signal-processing functions. The image rejecting microwave photonic downconveter incoming microwave signals can be processed without ambiguity in direction finding applications, allowing remotable, multioctave microwave signal processing for frequency and phase determination. A first laser providing an optical carrier that is modulated by a first electro-optic modulator with a sinusoidal electrical signal generated by a first local oscillator and a second laser providing optical carrier that is modulated by a second electro-optic modulator with a sinusoidal electrical signal generated by the second local oscillator for a signal generated by a second local oscillator; are transmitted independently through two polarization-maintaining (PM) optical fibers of arbitrary length to a distant point. There the first modulated optical signal is converted to an electrical domain and mixed with an input from an ultra-broadband radio frequency (RF) antenna receive-array, shifting the entire RF band to a higher frequency band equal to the original RF signal plus the modulated optical frequency signal.

US Patent:

7880172, Feb 1, 2011

Filed:

Jan 31, 2007

Appl. No.:

11/700268

Inventors:

Jason P. Henning - Carrboro NC, US
Allan Ward - Durham NC, US
Alexander Suvorov - Durham NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 29/15

US Classification:

257 77, 257192, 257213, 257201, 257E21054, 257E21056, 257E21057

Abstract:

A unit cell of a metal-semiconductor field-effect transistor (MESFET) includes a semi-insulating substrate having a surface, an implanted n-type channel region in the substrate, and implanted source and drain regions extending from the surface of the substrate into the implanted channel region. A gate contact is between the source and the drain regions, and an implanted p-type region is beneath the source region. The implanted p-type region has an end that extends towards the drain region, is spaced apart vertically from the implanted channel layer, and is electrically coupled to the source region. Methods of forming transistors including implanted channels and implanted p-type regions beneath the source region are also disclosed.

US Patent:

7915703, Mar 29, 2011

Filed:

May 13, 2009

Appl. No.:

12/465279

Inventors:

Jason Patrick Henning - Carrboro NC, US
Allan Ward - Durham NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 29/47

US Classification:

257471, 438 92, 438570, 257E2704, 257E29338, 257E21368

Abstract:

Fabrication of a Schottky diodes may include providing a Schottky contact layer containing a low barrier metal layer with spaced apart high barrier metal islands therein on a first surface of a substrate. A diode contact is formed on a second surface of the substrate that is opposite to the first surface. Formation of the Schottky contact layer may include providing a liquid mixture of a high barrier metal and a low barrier metal on the first surface of the substrate. Temperature and/or relative concentrations of the high and low barrier metals in the liquid mixture may be controlled to cause regions of the high barrier metal to solidify within the liquid mixture and agglomerate to form the spaced apart high barrier metal islands while inhibiting solidification of the low barrier metal. The temperature and relative concentrations may then be controlled to cause the low barrier metal to solidify and form the low barrier metal layer containing the high barrier metal islands.

US Patent:

8049272, Nov 1, 2011

Filed:

Apr 16, 2007

Appl. No.:

11/735799

Inventors:

Jason P. Henning - Carrboro NC, US
Allan Ward - Durham NC, US
Alexander Suvorov - Durham NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 29/666
H01L 29/78

US Classification:

257330, 257332, 428172

Abstract:

A MESFET includes a silicon carbide layer, spaced apart source and drain regions in the silicon carbide layer, a channel region positioned within the silicon carbide layer between the source and drain regions and doped with implanted dopants, and a gate contact on the silicon carbide layer. Methods of forming a MESFET include providing a layer of silicon carbide, forming spaced apart source and drain regions in the silicon carbide layer, implanting impurity atoms to form a channel region between the source and drain regions, annealing the implanted impurity atoms, and forming a gate contact on the silicon carbide layer.

US Patent:

20060006393, Jan 12, 2006

Filed:

Jul 6, 2004

Appl. No.:

10/884930

Inventors:

Allan Ward - Durham NC, US
Jason Henning - Carrboro NC, US
Helmut Hagleitner - Zebulon NC, US
Keith Wieber - Siler City NC, US

International Classification:

H01L 29/15

US Classification:

257077000

Abstract:

A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.

US Patent:

20060118792, Jun 8, 2006

Filed:

Jan 12, 2006

Appl. No.:

11/331325

Inventors:

Anant Agarwal - Durham NC, US
Allan Ward - Durham NC, US

International Classification:

H01L 31/0312

US Classification:

257077000

Abstract:

An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that at least partially surround a silicon carbide-based junction, an insulating layer on the floating guard rings, and a silicon carbide surface charge compensation region between the floating guard rings and adjacent the surface of the silicon carbide layer. A silicon nitride layer is on the silicon carbide layer, and an organic protective layer is on the silicon nitride layer. An oxide layer may be between the silicon nitride layer and the surface of the silicon carbide layer. Methods of forming edge termination structures are also disclosed.

US Patent:

20070001174, Jan 4, 2007

Filed:

Jun 29, 2005

Appl. No.:

11/169378

Inventors:

Zoltan Ring - Durham NC, US
Helmut Hagleitner - Zebulon NC, US
Jason Henning - Carrboro NC, US
Andrew Mackenzie - Cary NC, US
Scott Allen - Apex NC, US
Scott Sheppard - Chapel Hill NC, US
Richard Smith - Carrboro NC, US
Saptharishi Sriram - Cary NC, US
Allan Ward - Durham NC, US

International Classification:

H01L 29/15
H01L 31/0256

US Classification:

257076000

Abstract:

A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

US Patent:

20070001176, Jan 4, 2007

Filed:

Jan 10, 2006

Appl. No.:

11/328550

Inventors:

Allan Ward - Durham NC, US
Jason Henning - Carrboro NC, US

International Classification:

H01L 31/0312

US Classification:

257077000

Abstract:

An improved termination structure for high field semiconductor devices in silicon carbide is disclosed. The termination structure includes a silicon carbide-based device for high-field operation, an active region in the device, an edge termination passivation for the active region, in which the edge termination passivation includes, an oxide layer on at least some of the silicon carbide portions of the device for satisfying surface states and lowering interface density, a non-stoichiometric layer of silicon nitride on the oxide layer for avoiding the incorporation of hydrogen and for reducing parasitic capacitance and minimizing trapping, and, a stoichiometric layer of silicon nitride on the nonstoichiometric layer for encapsulating the nonstoichiometric layer and the oxide layer.