Allen Hanson

US Patent:

7247889, Jul 24, 2007

Filed:

Dec 3, 2004

Appl. No.:

11/004628

Inventors:

Allen W. Hanson - Cary NC, US
John Claassen Roberts - Hillsborough NC, US
Edwin L. Piner - Cary NC, US
Pradeep Rajagopal - Raleigh NC, US

Assignee:

Nitronex Corporation - Durham NC

International Classification:

H01L 31/00
H01L 21/28

US Classification:

257189, 257615, 257E33037, 257E33049, 438604

Abstract:

III-nitride material structures including silicon substrates, as well as methods associated with the same, are described. Parasitic losses in the structures may be significantly reduced which is reflected in performance improvements. Devices (such as RF devices) formed of structures of the invention may have higher output power, power gain and efficiency, amongst other advantages.

US Patent:

7566913, Jul 28, 2009

Filed:

Dec 4, 2006

Appl. No.:

11/634332

Inventors:

Robert J. Therrien - Apex NC, US
Jerry W. Johnson - Raleigh NC, US
Allen W. Hanson - Cary NC, US

Assignee:

Nitronex Corporation - Durham NC

International Classification:

H01L 33/00

US Classification:

257103, 257 98, 257191, 257192, 438285

Abstract:

Semiconductor structures comprising a III-nitride (e. g. , gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e. g. , gold) separated from certain other region(s) of the structure (e. g. , a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e. g. , FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

US Patent:

8026581, Sep 27, 2011

Filed:

Feb 5, 2008

Appl. No.:

12/025976

Inventors:

Allen W. Hanson - Cary NC, US
Edwin Lanier Piner - Cary NC, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 23/495
H01L 29/66

US Classification:

257675, 257 77, 257192, 257194, 257201, 257E29246, 257E29248, 257E29249

Abstract:

Gallium nitride material structures are provided, as well as devices and methods associated with such structures. The structures include a diamond region which may facilitate conduction and removal of heat generated within the gallium nitride material during device operation. The structures described herein may form the basis of a number of semiconductor devices and, in particular, transistors (e. g. , FETs).

US Patent:

8067786, Nov 29, 2011

Filed:

Jul 24, 2009

Appl. No.:

12/508891

Inventors:

Robert J. Therrien - Apex NC, US
Jerry W. Johnson - Raleigh NC, US
Allen W. Hanson - Cary NC, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 33/00

US Classification:

257103, 257191, 257194, 438285, 438478

Abstract:

Semiconductor structures comprising a III-nitride (e. g. , gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e. g. , gold) separated from certain other region(s) of the structure (e. g. , a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e. g. , FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

US Patent:

8288253, Oct 16, 2012

Filed:

Jun 30, 2011

Appl. No.:

13/173006

Inventors:

Allen W. Hanson - Cary NC, US
Anthony Kaleta - Lowell MA, US

Assignee:

M/A-COM Technology Solutions Holdings, Inc. - Lowell MA

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438478, 438 22, 438 48, 438167, 438169, 257E21002, 257E31127

Abstract:

A process for fabricating a semiconductor device. The process including (a) growing a channel layer on a buffer layer, (b) growing a barrier layer on the channel layer, (c) epitaxially growing a quaternary etch-stop layer on the barrier layer, (d) growing a first contact layer on the quaternary etch-stop layer, (e) growing a second contact layer on the first contact layer, (f) etching portions of the second contact layer to reveal a first recess surface, and (g) etching portions of the first contact layer to reveal a second recess surface. The second contact layer may be a highly doped contact layer. The second recess surface generally forms a gate region. The first and the second contact layers have a first etch rate and the quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.

US Patent:

8288260, Oct 16, 2012

Filed:

Jun 30, 2011

Appl. No.:

13/173015

Inventors:

Allen W. Hanson - Cary NC, US

Assignee:

M/A-COM Technology Solutions Holdings, Inc. - Lowell MA

International Classification:

H01L 21/28
H01L 21/44

US Classification:

438571, 438570, 438576, 257E21002, 257E21121, 257E31127

Abstract:

A process for fabricating a semiconductor device. The process includes (a) growing an n-channel layer of gallium arsenide (GaAs) on a buffer layer, (b) growing a barrier layer on the re-channel layer, (c) epitaxially growing a first etch-stop layer on the barrier layer, (d) growing a first contact layer of wide band-gap material on the first etch-stop layer, (e) epitaxially growing a second etch-stop layer on the first contact layer, (f) growing a second contact layer on the second etch-stop layer, where the second contact layer is a highly doped material, and (g) selectively etching portions of the first contact layer, the second etch-stop layer, and the second contact layer to form a gate region.

US Patent:

8343856, Jan 1, 2013

Filed:

Nov 22, 2011

Appl. No.:

13/303075

Inventors:

Robert J. Therrien - Apex NC, US
Jerry W. Johnson - Raleigh NC, US
Allen W. Hanson - Cary NC, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438479, 438285, 438478, 257103, 257191

Abstract:

Semiconductor structures comprising a III-nitride (e. g. , gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e. g. , gold) separated from certain other region(s) of the structure (e. g. , a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e. g. , FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

US Patent:

8350288, Jan 8, 2013

Filed:

Nov 22, 2011

Appl. No.:

13/303109

Inventors:

Robert J. Therrien - Apex NC, US
Jerry W. Johnson - Raleigh NC, US
Allen W. Hanson - Cary NC, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 33/00

US Classification:

257103, 257 76, 257191, 438285, 438478

Abstract:

Semiconductor structures comprising a III-nitride (e. g. , gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e. g. , gold) separated from certain other region(s) of the structure (e. g. , a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e. g. , PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.