Anthony Francis Quaglietta - Methuen MA Allen William Hanson - Pepperell MA Thomas Aaron Winslow - Roanoke VA
Assignee:
M/A-Com, Inc. - Lowell MA
International Classification:
H01L 310328
US Classification:
257197, 257276, 257565, 257571, 257579
Abstract:
A semiconductor amplifier includes collector straps that form air bridges over a set of transistors and make parallel electrical connections between the collectors of the transistor and collector contact pad. Base straps establish base bias and electrically connect a dc current source with bases of the transistors through resistive elements.
Structure And Process For Improving High Frequency Isolation In Semiconductor Substrates
Kenneth Vern Buer - Pepperell MA Anthony Francis Quaglietta - Methuen MA Allen Hanson - Pepperell MA
Assignee:
The Whitaker Corporation - Wilmington DE
International Classification:
H01L 2980
US Classification:
257275, 257276, 438381, 438423
Abstract:
An isolation structure for high frequency integrated circuits is a conductive material disposed over a region of active gallium arsenide substrate. The conductive material over the active region creates a lossy RF path to reduce undesired coupling between adjacent conductors. In one case, two RF signal lines ( ) terminated at the same via pad ( ) have weaker coupling than in prior art via structures due to the lossy RF structure disposed on isolating fractional portions ( ) of the via pad ( ). The isolating fractional portion ( ) are intermediate terminating fractional portions ( ) of the via pad ( ) to which the signal lines ( ) are connected. In another case, two parallel bias lines ( ) are disposed over an active layer region ( ) increasing the RF loss between them and advantageously reducing the RF coupling. The reduced RF coupling improves RF isolation and permits increased miniaturization.
Process For Selective Recess Etching Of Epitaxial Field Effect Transistors With A Novel Etch-Stop Layer
A process for selective recess etching of GaAs field-effect transistors. A selected etch stop layer (In. sub. x Ga. sub. 1-x P) maintains what is commonly referred to as lattice-match with the GaAs substrate material. By using this etch stop, a significant reduction in access resistances is realized with respect to devices containing other etch stop materials while an improvement in the uniformity of device characteristics across the wafer and from wafer to wafer is realized.
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