Allen V Ho

US Patent:

43859755, May 31, 1983

Filed:

Dec 30, 1981

Appl. No.:

6/336109

Inventors:

Allen P. Ho - Sunnyvale CA
Cheng T. Horng - San Jose CA
Bernard M. Kemlage - Kingston NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

C23C 1500

US Classification:

204192E

Abstract:

A method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate by forming a wide plug of chemical vapor deposited silicon dioxide in the trench, filling the remaining unfilled trench portions by chemical vapor depositing a layer of silicon dioxide over the substrate and etching back this layer. The method produces chemically pure, planar wide deep dielectric filled isolation trenches and may also be used to simultaneously produce narrow deep dielectric filled isolation trenches.

US Patent:

54148200, May 9, 1995

Filed:

Mar 21, 1994

Appl. No.:

8/215232

Inventors:

Harold L. McFarland - San Jose CA
Allen P. Ho - Fremont CA

Assignee:

NexGen, Inc. - Milpitas CA

International Classification:

G06F 1336
G06F 1340

US Classification:

395325

Abstract:

A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only. If the ABI is unable to do the crossing transfer because the AB was busy, the ABI automatically causes the NexBus adapter to retry the request using the -AREQ line. Thus the slower AB is only accessed when actually necessary.

US Patent:

53697480, Nov 29, 1994

Filed:

Aug 23, 1991

Appl. No.:

7/748768

Inventors:

Harold L. McFarland - San Jose CA
Allen P. Ho - Fremont CA

Assignee:

Nexgen Microsystems - Milpitas CA

International Classification:

G06F 1336

US Classification:

395325

Abstract:

A dual-bus architecture that includes a high-seed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only. If the ABI is unable to do the crossing transfer because the AB was busy, the ABI automatically causes the NexBus adapter to retry the request using the -AREQ line. Thus the slower AB is only accessed when actually necessary.

US Patent:

56279760, May 6, 1997

Filed:

Mar 20, 1995

Appl. No.:

8/407309

Inventors:

Harold L. McFarland - San Jose CA
Allen P. Ho - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

395308

Abstract:

A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only. If the ABI is unable to do the crossing transfer because the AB was busy, the ABI automatically causes the NexBus adapter to retry, the request using the -AREQ line. Thus the slower AB is only accessed when actually necessary.