Allen M Roberts

US Patent:

55420621, Jul 30, 1996

Filed:

Dec 22, 1993

Appl. No.:

8/172684

Inventors:

George S. Taylor - Menlo Park CA
P. Michael Farmwald - Berkeley CA
Timothy P. Layman - San Carlos CA
Huy X. Ngo - Santa Clara CA
Allen W. Roberts - Union City CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

B06F 1208

US Classification:

395403

Abstract:

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

US Patent:

53074777, Apr 26, 1994

Filed:

May 10, 1993

Appl. No.:

8/059715

Inventors:

George S. Taylor - Menlo Park CA
P. Michael Farmwald - Berkeley CA
Timothy P. Layman - San Carlos CA
Huy X. Ngo - Santa Clara CA
Allen W. Roberts - Union City CA

Assignee:

Mips Computer Systems, Inc. - Sunnyvale CA

International Classification:

G06F 1208

US Classification:

395425

Abstract:

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

US Patent:

50561103, Oct 8, 1991

Filed:

Dec 11, 1989

Appl. No.:

7/448715

Inventors:

Timonty S. Fu - Fremont CA
Allen W. Roberts - Union City CA

Assignee:

MIPS Computer Systems, Inc. - Sunnyvale CA

International Classification:

H04B 356

US Classification:

375 36

Abstract:

A solution to the problem in differential buses that the bus state for a given line pair is undefined when no unit is driving either of the bus lines in the pair. The lines in the bus pair are terminated to different voltage levels, thereby establishing a desired default condition when no unit is driving either line. The voltage offset between the two bus lines must be sufficient that differential receivers coupled to the bus when the bus is not driven can respond to the offset. At the same time, the offset must not be so great that a driver attempting to drive the bus pair cannot overcome the offset with enough margin for the receivers.

US Patent:

44816251, Nov 6, 1984

Filed:

Oct 21, 1981

Appl. No.:

6/313524

Inventors:

Allen W. Roberts - Union City CA
Harold L. McFarland - Santa Clara CA
Harlan Lau - Campbell CA

Assignee:

Elxsi - San Jose CA

International Classification:

H04J 312

US Classification:

370 85

Abstract:

In a high speed data bus system, each functional unit has an associated port which operates to accept all related information that makes up a communication, or if this cannot be done, to accept none of the information. More particularly, an information transfer, depending on its nature, may comprise one BIQ or more than one BIQ (a "BIQ" is a bus information quantum which is placed on the bus for one bus cycle). To implement the indivisibility of multiple-BIQ transfers, the control logic for each port includes screening circuitry responsive to the state of the port's input buffers, and further responsive to flags from the functional unit for selectively accepting or rejecting BIQ's, and further includes screening constraint circuitry to ensure that the port accepts all or none of the BIQ's that make up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers (for example, operations).

US Patent:

56995512, Dec 16, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/484313

Inventors:

George S. Taylor - Menlo Park CA
P. Michael Farmwald - Berkeley CA
Timothy P. Layman - San Carlos CA
Huy Xuan Ngo - Santa Clara CA
Allen W. Roberts - Union City CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1200

US Classification:

395471

Abstract:

A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.

US Patent:

47060778, Nov 10, 1987

Filed:

Sep 8, 1981

Appl. No.:

6/300349

Inventors:

Allen M. Roberts - Manhattan Beach CA
Andrew Sangster - Redondo Beach CA
Zoltan Stroll - Rancho Palos Verdes CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G09G 100
G09G 300

US Classification:

340728

Abstract:

A circuit for producing a "knight ordered dither" halftone pattern for a CRT and a "double spiral" halftone pattern for a xerographic printer is described. The circuit comprises a RAM for storing the threshold values, a comparator, and supporting addressing and logic parts. Also described are a program for allowing the operator to interactively generate threshold patterns, and several knight tour patterns specifically designed for a CRT using interlaced rasters.