Abbas A Amirichimeh

US Patent:

7545899, Jun 9, 2009

Filed:

Mar 31, 2004

Appl. No.:

10/813235

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
John Louie - Huntington Beach CA, US
Vasudevan Parthasarathy - Irvine CA, US
Linda Ying - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00
H04L 25/40

US Classification:

375358, 375371

Abstract:

Systems and methods for synchronizing a receive clock signal phase with a transmit clock signal phase are presented. A system includes a receiving channel and a transmitting channel, wherein the transmitting channel synchronizes a transmit clock signal phase with a receive clock signal phase based on receive clock signal phase data. A method includes storing a previous receive clock signal phase of a receiving channel and identifying a current receive clock signal phase of the receiving channel. The method further includes determining a phase difference between the previous receive clock signal phase and the current receive clock signal phase, and identifying a direction of the phase difference. The method further includes adjusting a previous transmit clock signal phase of the transmitting channel to a current transmit clock signal phase of the transmitting channel based on the phase difference and direction.

US Patent:

7593457, Sep 22, 2009

Filed:

Mar 31, 2004

Appl. No.:

10/813363

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
John Louie - Huntington Beach CA, US
Vasudevan Parthasarathy - Irvine CA, US
Linda Ying - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/38
H04L 7/00

US Classification:

375219, 375220, 375356

Abstract:

A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

US Patent:

7796682, Sep 14, 2010

Filed:

Jun 1, 2009

Appl. No.:

12/476207

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
John Louie - Huntington Beach CA, US
Vasudevan Parthasarathy - Irvine CA, US
Linda Ying - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 25/20
H04L 7/00
H04B 1/38

US Classification:

375211, 375219, 375220, 375356

Abstract:

A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

US Patent:

8094590, Jan 10, 2012

Filed:

Oct 17, 2008

Appl. No.:

12/253851

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
Dwight Oda - Cypress CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 13/10

US Classification:

370304

Abstract:

A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit. Preferably, the set of interconnects includes a first interconnect to convey the first bit and a second interconnect to convey the second bit.

US Patent:

8111738, Feb 7, 2012

Filed:

Sep 13, 2010

Appl. No.:

12/881108

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
John Louie - Huntington Beach CA, US
Vasudevan Parthasarathy - Irvine CA, US
Linda Ying - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/38
H04L 7/00
H04L 23/00

US Classification:

375219, 375358, 375376

Abstract:

A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

US Patent:

8532163, Sep 10, 2013

Filed:

Feb 6, 2012

Appl. No.:

13/367282

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
John Louie - Huntington Beach CA, US
Vasudevan Parthasarathy - Irvine CA, US
Linda Ying - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/38
H04L 7/00
H03D 3/24

US Classification:

375219, 375358, 375373

Abstract:

A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

US Patent:

20040141497, Jul 22, 2004

Filed:

Oct 29, 2003

Appl. No.:

10/695498

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
Dwight Oda - Cypress CA, US

International Classification:

H04Q011/00

US Classification:

370/362000

Abstract:

A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce said signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. The signal is capable of being represented as a series of characters. A character is capable of being represented as a first data bit, a second data bit, and a control bit. A first interconnect is configured to convey the first data bit. A second interconnect is configured to convey the second data bit. A third interconnect is configured to convey the control bit. The third interconnect is positioned substantially between the first interconnect and the second interconnect.

US Patent:

20040141531, Jul 22, 2004

Filed:

Oct 29, 2003

Appl. No.:

10/695458

Inventors:

Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
Dwight Oda - Cypress CA, US

International Classification:

H04J003/04

US Classification:

370/535000

Abstract:

A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit. Preferably, the set of interconnects includes a first interconnect to convey the first bit and a second interconnect to convey the second bit. The lengths of the first and the second interconnects are substantially equal.