Amy Xiaofang Yang

US Patent:

6735749, May 11, 2004

Filed:

Mar 21, 2002

Appl. No.:

10/103521

Inventors:

Mu-Jing Li - Sunnyvale CA
Amy Yang - Saratoga CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5, 703 1, 716 2, 716 11

Abstract:

Method and apparatus for checking integrated circuit designs. In particular, one embodiment of the present invention is a method that for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of: (a) growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object; (b) performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and (c) identifying checks relating to the rectangular boxes.

US Patent:

6769099, Jul 27, 2004

Filed:

Apr 12, 2002

Appl. No.:

10/121322

Inventors:

Mu-Jing Li - Sunnyvale CA
Amy Yang - Saratoga CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 2, 716 4

Abstract:

A method, apparatus and computer program product for checking of integrated circuit design files using rules files. Each of the rules files has a rule associated therewith. The rules are sequentially compared with objects associated with the design files in an object-to-check-pool (OTCP). The sequence in which the rules are compared to objects in the OTCP is arrange to maximize a probability of determining whether design characteristics of the objects in the OTCP satisfies all rules associated with the rules files while minimizing a number of rules that must be compared with the OTCP.

US Patent:

6804808, Oct 12, 2004

Filed:

Sep 30, 2002

Appl. No.:

10/260817

Inventors:

Mu-Jing Li - Sunnyvale CA
Amy Yang - Saratoga CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4

Abstract:

A redundant via design rule check is preferably performed on multi-wide object class design layouts to ensure that each connection area between two conductive layers has at least a certain number of vias and/or has vias placed appropriately to reduce the risk of via failure due to vacancy concentration of isolated vias. In exemplary embodiments, a redundant via design rule check preferably ensures that for vias placed within a connection area of a metal feature (or within a localized region of a larger metal geometry) that is both greater than a certain width and greater than a certain area in size, the vias are both sufficient in number and/or suitable in their location. Vias located inside a geometry but falling outside a virtual edge of a wide class object may be included to satisfy exemplary rules.

US Patent:

6871332, Mar 22, 2005

Filed:

Sep 30, 2002

Appl. No.:

10/260813

Inventors:

Mu-Jing Li - Sunnyvale CA, US
Amy Yang - Saratoga CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F017/50

US Classification:

716 5, 716 2

Abstract:

Manipulation of a multi-wide object class design layout to facilitate design rule checking or automatic correction of design rule errors is improved by deriving wide class objects from geometries of the design layout, and applying certain rules to non-virtual boundaries of the wide class objects that are not applied to virtual boundaries of the wide class objects. In an exemplary embodiment, the wide class objects are preferably derived by sizing down, then sizing up, each geometry by a sizing factor equal to half the minimum width of the particular wide class object less an amount that preferably corresponds to that represented by a minimum resolution of the design layout. Portions of a geometry that are otherwise excluded as being too narrow in width, but that lie wholly within a correction factor of the boundary of the wide class object otherwise derived, are preferably included to form effective wide class objects.

US Patent:

6883149, Apr 19, 2005

Filed:

Sep 30, 2002

Appl. No.:

10/260811

Inventors:

Mu-Jing Li - Sunnyvale CA, US
Amy Yang - Saratoga CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F017/50

US Classification:

716 4, 716 1, 716 5, 716 6, 716 8, 716 10, 716 12, 716 14

Abstract:

In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks against the non-virtual boundaries of a wide class object, and not against the virtual boundaries. An exemplary embodiment provides a method for identifying as a violation, for each wide class wobject, any geometry on another layer which is located at least partially inside the wobject and has any portion thereof located within a distance enclof any non-virtual boundary of the wobject. The exemplary method is preferably performed using effective wide class objects.

US Patent:

6892368, May 10, 2005

Filed:

Feb 26, 2003

Appl. No.:

10/374948

Inventors:

Mu-Jing Li - Sunnyvale CA, US
Amy Yang - Saratoga CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F017/50

US Classification:

716 5, 716 4

Abstract:

Automated patching techniques to correct certain rule violations are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. A series of patches of predefined orientations are utilized to correct design rule violations. A set of violations are identified, patches of a predefined orientation are attempted to correct one or more violations. Patches of another predefined orientation are attempted to correct remaining violations. Attempted patching is repeated until all patches in the series have been attempted or all violations have been corrected. Patches can be added to a construction layer over the set of violations, and each patch that does not cause a design rule violation can be copied to a metal layer. A series of patches of predefined orientations are used, efficiently correcting design rule violations such as minimum area and jog rule violations.

US Patent:

6578201, Jun 10, 2003

Filed:

Nov 20, 1998

Appl. No.:

09/197270

Inventors:

Tobie J. LaRocca - San Jose CA
Amy Yang - San Jose CA
Gregory A. Erickson - San Francisco CA

Assignee:

Diva Systems Corporation - Redwood City CA

International Classification:

H04N 7173

US Classification:

725 86, 725 61, 725135, 725140, 709201, 709231

Abstract:

A multimedia stream incorporating interactive support for multiple types of subscriber terminals. The multimedia stream is created by multiplexing several component streams. The component streams include a video stream, an audio stream, and an interactive data stream. The interactive data stream includes data specific to different types of subscriber terminals multiplexed together.

US Patent:

20220304286, Sep 29, 2022

Filed:

Jun 16, 2020

Appl. No.:

17/617878

Inventors:

- Los Angeles CA, US
Moise Danielpour - Los Angeles CA, US
Gi Bum Kim - North Hollywood CA, US
Amy Yang - Los Angeles CA, US

Assignee:

CEDARS-SINAI MEDICAL CENTER - Los Angeles CA

International Classification:

A01K 67/027
C12N 15/10
C12N 15/86
C12N 15/90

Abstract:

Described herein are donor vectors and systems for use in dual recombinase-mediated cassette exchange. Also described herein are animal models and human cells for consistent, rigorous, and facile investigation of transgene expression. Further described herein are methods of screening for therapeutic drugs using these animal models, and methods of treatment.