Anand J Janaswamy

US Patent:

20100101634, Apr 29, 2010

Filed:

Sep 10, 2009

Appl. No.:

12/557436

Inventors:

CHRISTOPHER FRANK - Rough and Ready CA, US
John Montello - El Cajon CA, US
Christopher S. Gopal - La Jolla CA, US
Mike Curtis - Temewia CA, US
Anand Janaswamy - Cardiff CA, US
Mark Farrelly - Carlsbad CA, US

International Classification:

H01L 31/048
H05K 13/00

US Classification:

136251, 295921

Abstract:

The present invention is directed toward apparatuses, systems and methods for solar panels capable of rooftop installation. In some embodiments, a low profile solar panel is provided, comprising: a solar laminate; and a flexible material sheet adhered to the solar laminate, wherein the flexible material sheet is configured to operate as a frame that supports and houses the solar laminate. In some such embodiments, the low profile solar panel further comprises a secondary sheet, wherein the secondary sheet is disposed on an edge formed by adhering the flexible material sheet to the solar laminate.

US Patent:

20100294341, Nov 25, 2010

Filed:

Feb 2, 2010

Appl. No.:

12/698850

Inventors:

CHRISTOPHER FRANK - Penn Valley CA, US
John Montello - El Cajon CA, US
Chris Gopal - La Jolla CA, US
Mike Curtis - Temecula CA, US
Anand Janaswamy - Cardiff CA, US
Mark Farrelly - Carlsbad CA, US

International Classification:

H01L 31/048
H01L 31/0203
B32B 37/12

US Classification:

136251, 136259, 156 60

Abstract:

The present invention is directed toward apparatus and methods for solar panels capable of rooftop installation. In some embodiments, a low profile solar laminate is provided, comprising: a base layer; a photovoltaic layer; a semi-rigid panel; an ultraviolet resistant layer; wherein a first adhesive adheres the base layer to the semi-rigid panel, a second adhesive adheres the semi-rigid panel to the photovoltaic layer, and a third adhesive adheres the ultraviolet resistant layer to the photovoltaic layer.

US Patent:

20110240337, Oct 6, 2011

Filed:

Apr 5, 2010

Appl. No.:

12/754588

Inventors:

John Montello - El Cajon CA, US
Mark Farrelly - Carlsbad CA, US
Anand Janaswamy - Cardiff CA, US
Mike Curtis - Temecula CA, US

International Classification:

H01B 5/00
H01L 31/048

US Classification:

1741261, 136251

Abstract:

Various embodiments of the invention provide an interconnect designed to be placed between layers of a photovoltaic laminate, and that has built-in in-plane stress relief features. In accordance with various embodiments, the interconnect, once implemented into a photovoltaic laminate, can withstand at least 200 temperature cycles, as is required by certain certifying bodies, without suffering failure. According to one embodiment of the present invention, an interconnect is provided for connecting a first photovoltaic cell to the bus array or a second photovoltaic cell within a photovoltaic laminate, the interconnect comprising: a single conductive wire having a cross-section sufficient for placement between layers of a photovoltaic laminate; wherein the single conductive wire comprises a stress-relief feature, and the stress-relief feature enables the interconnect to maintain a connection between the first photovoltaic cell and the bus array or the second photovoltaic cell while absorbing stress induced by a change in position of the first photovoltaic cell relative to a position of the bus array or the second photovoltaic cell.

US Patent:

20120080078, Apr 5, 2012

Filed:

Oct 2, 2010

Appl. No.:

12/896843

Inventors:

Mark Farrelly - Carlsbad CA, US
Anand Janaswamy - Cardiff CA, US
Shewit Agaskar - San Diego CA, US
John Montello - San Diego CA, US

Assignee:

APPLIED SOLAR, LLC - San Diego CA

International Classification:

H01L 31/048
H01L 31/02

US Classification:

136251, 438 66, 257E31113

Abstract:

Photovoltaic (PV) crystalline silicon modules and methods of manufacturing wherein the modules contain a non-glass front sheet, upper and lower encapsulate layers, a PV cell layer, an insulating sheet, and a structural back plane comprising an aluminum composite. The front sheet can be comprised of ETFE, the encapsulate layers comprise EVA, and the back plane preferably comprises APA. This particular configuration results in a lightweight PV module that still retains a high power density, and can be readily installed onto rooftops without traditional heavy racking. The PV module may be adhered to the roof using a double sided pressure sensitive adhesive or heat welded.

US Patent:

55026320, Mar 26, 1996

Filed:

Jul 15, 1994

Appl. No.:

8/275569

Inventors:

Leo F. P. Warmerdam - Nijmegen, NL
Anand Janaswamy - Sunnyvale CA

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H02M 324
H02M 3335

US Classification:

363 98

Abstract:

A half-bridge driver circuit including a lower drive module and a floating upper drive module for driving respective external upper and lower power transistors of a high voltage half bridge is contained in an integrated circuit chip which includes an on-chip bootstrap diode emulator for charging an external bootstrap capacitor that powers the upper drive module. The upper drive is accommodated in an insulated well and the diode emulator includes as its main current carrying element, a LDMOS transistor formed along the periphery of the well. The LDMOS transistor is driven into a conducting state at the same time the lower power transistor is driven into a conducting state. A clamp and current source solidly bias the backate of the LDMOS while limiting the current drawn by a parasitic transistor attached to the backgate during startup of the LDMOS.

US Patent:

56662807, Sep 9, 1997

Filed:

Dec 27, 1995

Appl. No.:

8/579654

Inventors:

Anand Janaswamy - Sunnyvale CA
Rajsekhar Jayaraman - Rancho Palos Verdes CA
Michael Amato - Albuquerque NM
Paul R. Veldman - Oss, NL

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H02M 324
H02M 3335

US Classification:

363 98

Abstract:

A half-bridge driver circuit including a lower drive module and a floating upper drive module for driving respective external upper and lower power transistors of a high voltage half bridge is contained in an integrated circuit chip which includes an on-chip bootstrap diode emulator which is turned on in response to a control signal applied to its gate in order to pass current from a power supply to charge an external bootstrap capacitor that powers the upper drive module. The upper drive module is accommodated in an insulated well and the diode emulator includes as its main current carrying element, a JFET transistor formed along the periphery of the well. The JFET transistor is driven into a conducting state at the same time the lower power transistor is driven into a conducting state. The source electrode of the JFET is coupled to the power supply via a diode, such that the voltage at said source electrode cannot rise above a level which is one diode drop below the voltage at said power supply output and control circuitry derives the control control signal in a manner that it is constrained not to rise a level which is three diode drops below the voltage at the power supply output and limits the current that may flow in the gate electrode.

US Patent:

53734351, Dec 13, 1994

Filed:

Nov 19, 1993

Appl. No.:

8/155053

Inventors:

Rajsekhar Jayaraman - Rancho Palas Verdes CA
Anand Janaswamy - Ossining NY
Thor Wacyk - Briarcliff Manor NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H02M 324

US Classification:

363 98

Abstract:

A half-bridge driver circuit including a lower drive module and a floating upper drive module for driving respective external upper and lower power transistors of a high voltage half bridge is contained in an integrated circuit chip which includes an on-chip bootstrap diode emulator for charging an external bootstrap capacitor that powers the upper drive module. The upper drive is accommodated in an insulated well and the diode emulator includes as its main current carrying element, a LDMOS transistor formed along the periphery of the well. The LDMOS transistor is driven into a conducting state at the same time the lower power transistor is driven into a conducting state.