Anand Meruva

Senior Staff Mixed Signal Design Engineer

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Location:

San Diego, CA

Industry:

Semiconductors

Work:

Qualcomm
Senior Staff Mixed Signal Design Engineer
Arizona State University Jan 2006 - Dec 2007
Graduate Research Assistant

Education:

Arizona State University 2005 - 2007
Master of Science, Masters, Electrical Engineering Goka Raju Ranga Raju Institute of Engineering & Technology 2001 - 2005

Skills:

Mixed Signal
Circuit Design
Verilog
Cadence Virtuoso
Analog Circuit Design
Vlsi
Semiconductors
Analog
Asic
Ic
Cmos
Debugging
Systemverilog
Soc
Integrated Circuit Design
Vhdl
Rtl Design

Mixed Signal Design Engineer At Qualcomm

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Position:

Mixed Signal Design Senior Engineer at Qualcomm

Location:

Greater San Diego Area

Industry:

Semiconductors

Work:

Qualcomm since Jan 2008
Mixed Signal Design Senior Engineer
Arizona State University Jan 2006 - Dec 2007
Graduate Research Assistant

Education:

Arizona State University 2005 - 2007
MS, Electrical Engineering Gokaraju Rangaraju Institute of Engineering & Technology 2001 - 2005
B. Tech, Electronics and Communication Engineering

Honor & Awards:

Book: B. Jalali-Farahani, A. Meruva, M. Ismail, Digital Background Calibration of Analog to Digital Converters, publisher: Springer, in print in 2009 Papers: “A 14-b 32MS/s Pipelined ADC with fast convergence comprehensive background calibration”, Journal of Analog Integrated Circuits and Signal Processing, accepted for publication, November 2009. “A 14-b 32MS/s Pipelined ADC with fast convergence comprehensive background calibration”, submitted to International Symposium on Circuits and Systems, September 2009. “Low power high performance digitally assisted Pipelined ADC”, IEEE Annual Symposium on VLSI, pp. 111-116, April 2008. “A comprehensive calibration scheme for a 14-b 50 MSPS Pipeline ADC for multi-mode Wireless receivers”, IEEE International Midwest Symposium on Circuits and Systems, August 2007. “Digital background calibration of higher order nonlinearities in pipelined ADCs”, IEEE international symposium on circuits and systems (ISCAS), pp. 1233-1236, May 2007.