Anda C Mocuta

US Patent:

6509241, Jan 21, 2003

Filed:

Dec 12, 2000

Appl. No.:

09/734754

Inventors:

Heemyong Park - LaGrangeville NY
Anda C. Mocuta - Wappingers Falls NY
Paul A. Ronsheim - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438303, 438305, 438307, 257336

Abstract:

A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surface of the silicon substrate is formed by anisotropically etching the first surface of the silicon substrate to remove a portion of the material from the substrate. Both the first and second halo regions are formed by low-energy ion implantation. For the fabrication of an n-channel device, boron is implanted at an energy of no more than about 1 keV. Upon implantation and a subsequent annealing process, the first and second halo regions form a continuous halo region within the semiconductor substrate.

US Patent:

6635517, Oct 21, 2003

Filed:

Aug 7, 2001

Appl. No.:

09/924014

Inventors:

Tze-Chiang Chen - Yorktown Heights NY
Thomas T. Hwang - Wappingers Falls NY
Mukesh V. Khare - White Plains NY
Effendi Leobandung - Wappingers Falls NY
Anda C. Mocuta - LaGrangeville NY
Paul A. Ronsheim - Hopewell Junction NY
Ghavam G. Shahidi - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21335

US Classification:

438143, 438 58, 438402, 438411, 438473

Abstract:

A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.

US Patent:

6746924, Jun 8, 2004

Filed:

Feb 27, 2003

Appl. No.:

10/248884

Inventors:

Byoung H. Lee - Wappingers Falls NY
Anda C. Mocuta - LaGrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21335

US Classification:

438286, 438303, 438595, 438757

Abstract:

A method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design or tuning of the source and drain extension implant dose as well as its spacing from the gate. A photoresist mask is formed over at least a portion of each drain region, followed by an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and at least one sidewall of the gate conductor from damage by the angled ion implant which selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor. Then damaged portions of the nitride layer are removed while leaving undamaged portions of the nitride layer as a nitride mask to protect at least a portion of each drain region and at least one gate sidewall from a subsequent dopant implant, which is performed into the source regions and the drain regions while using the undamaged portions of the nitride layer as a mask to form the asymmetric extension MOSFET device. In some embodiments the nitride mask can be etched to form drain side spacers to provide different spacings for the source and drain extension ion implants.

US Patent:

6762469, Jul 13, 2004

Filed:

Apr 19, 2002

Appl. No.:

10/127196

Inventors:

Anda C. Mocuta - LaGrangeville NY
Meikei Ieong - Wappingers Falls NY
Ricky S. Amos - Rhinebeck NY
Diane C. Boyd - LaGrangeville NY
Dan M. Mocuta - LaGrangeville NY
Huajie Chen - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257407, 257391, 257392, 257376, 257402, 257204, 257 69, 257327, 257332, 438217, 438300, 438197, 438301, 438303

Abstract:

High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (Ë500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

US Patent:

6881635, Apr 19, 2005

Filed:

Mar 23, 2004

Appl. No.:

10/708746

Inventors:

Dureseti Chidambarrao - Weston CT, US
Effendi Leobandung - Wappingers Falls NY, US
Anda C. Mocuta - LaGrangeville NY, US
Haining S. Yang - Wappingers Falls NY, US
Huilong Zhu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/336
H01L021/20
H01L021/36
C30B023/00

US Classification:

438300, 438299, 438303, 438489

Abstract:

A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

US Patent:

6916698, Jul 12, 2005

Filed:

Mar 8, 2004

Appl. No.:

10/795672

Inventors:

Anda C. Mocuta - LaGrangeville NY, US
Meikei Ieong - Wappingers Falls NY, US
Ricky S. Amos - Rhinebeck NY, US
Diane C. Boyd - LaGrangeville NY, US
Dan M. Mocuta - LaGrangeville NY, US
Huajie Chen - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/8238

US Classification:

438217, 438223, 438224

Abstract:

High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

US Patent:

7056782, Jun 6, 2006

Filed:

Feb 25, 2004

Appl. No.:

10/786901

Inventors:

Ricky S. Amos - Rhinebeck NY, US
Diane C. Boyd - LaGrangeville NY, US
Cyril Cabral, Jr. - Mahopac NY, US
Richard D. Kaplan - Wappingers Falls NY, US
Jakub T. Kedzierski - Peekskill NY, US
Victor Ku - Tarrytown NY, US
Woo-Hyeong Lee - Poughquag NY, US
Ying Li - Poughkeepsie NY, US
Anda C. Mocuta - LaGrangeville NY, US
Vijay Narayanan - New York NY, US
An L. Steegen - Stanford CT, US
Maheswaran Surendra - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438199

Abstract:

The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

US Patent:

7067400, Jun 27, 2006

Filed:

Sep 17, 2004

Appl. No.:

10/943354

Inventors:

Stephen W. Bedell - Wappingers Falls NY, US
Anda C. Mocuta - LaGrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438479, 438483, 438967

Abstract:

A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.