Andrew C Anderson

US Patent:

6345009, Feb 5, 2002

Filed:

Sep 8, 2000

Appl. No.:

09/658465

Inventors:

Ely K. Tsern - Los Altos CA
Richard M. Barth - Palo Alto CA
Paul G. Davis - San Jose CA
Craig E. Hampel - San Jose CA
Thomas J. Holman - Portland OR
Andrew V. Anderson - Portland OR

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G11C 700

US Classification:

365222, 365120, 711106

Abstract:

A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.

US Patent:

6378018, Apr 23, 2002

Filed:

Oct 9, 1998

Appl. No.:

09/169506

Inventors:

Ely K. Tsern - Los Altos CA
Thomas J. Holman - Portland OR
Richard M. Barth - Palo Alto CA
Andrew V. Anderson - Portland OR
Paul G. Davis - San Jose CA
Craig E. Hampel - San Jose CA
Donald C. Stark - Los Altos CA
Abhijit M. Abhyankar - Sunnyvale CA

Assignee:

Intel Corporation - Santa Clara CA
Rambus, Inc. - Los Altos CA

International Classification:

G06F 1300

US Classification:

710129, 710128, 713323, 713320, 711105, 711 5

Abstract:

A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure.

US Patent:

6738400, May 18, 2004

Filed:

Jan 5, 1996

Appl. No.:

08/583387

Inventors:

Jerome P. Hall - Livermore CA
Terry W. Alger - Tracy CA
Andrew T. Anderson - Livermore CA
Phillip A. Arnold - Livermore CA

Assignee:

The United States of America as represented by the United States Department of Energy - Washington DC

International Classification:

H01S 322

US Classification:

372 36, 372 56, 372 62

Abstract:

A cooling structure ( ) for use inside a ceramic cylindrical tube ( ) of a metal vapor laser ( ) to cool the plasma in the tube ( ), the cooling structure ( ) comprising a plurality of circular metal members ( ) and mounting members ( ) that position the metal members ( ) coaxially in the tube ( ) to form an annular lasing volume, with the metal members ( ) being axially spaced from each other along the length of the tube ( ) to prevent the metal members from shorting out the current flow through the plasma in the tube ( ) and to provide spaces through which the heat from localized hot spots in the plasma may radiate to the other side of the tube ( ).

US Patent:

7346647, Mar 18, 2008

Filed:

Apr 15, 2003

Appl. No.:

10/417028

Inventors:

Gregory L. Bodine - Long Grove IL, US
Andrew J. Anderson - Broomfield CO, US
John P. Kane - Saint James NY, US

Assignee:

Computer Associates Think, Inc. - Islandia NY

International Classification:

G06F 15/16

US Classification:

709201, 709205, 709206, 709202

Abstract:

A system and method for providing a consistent interface with different system products or software solutions includes one or more system units or machines wherein the different system products or software solutions (instruments) reside. A service request can be made to an instrument gateway associated with a particular system unit or machine that includes an instrument that can service the request. The instrument gateway selects an instrument sponsor associated with that particular instrument to invoke the requested service from that particular instrument.

US Patent:

8607228, Dec 10, 2013

Filed:

Aug 8, 2006

Appl. No.:

11/501632

Inventors:

Erik C. Cota-Robles - Mountain View CA, US
Gilbert Neiger - Portand OR, US
Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/455
G06F 9/46

US Classification:

718 1, 718100, 718102, 718104

Abstract:

Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is store a counter enable indicator. The counter enable logic is to enable the counter, based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to a guest.

US Patent:

20080163254, Jul 3, 2008

Filed:

Dec 29, 2006

Appl. No.:

11/618446

Inventors:

Erik C. Cota-Robles - Mountain View CA, US
Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Hillsboro OR, US
Sebastian Schoenberg - Hillsboro OR, US

International Classification:

G06F 3/00

US Classification:

719318

Abstract:

Embodiments of apparatuses, methods, and systems for controlling virtual machines based on performance counters are disclosed. In one embodiment, an apparatus includes an event counter, a comparator, and virtualization control logic. The event counter is to keep an event count based on the number of occurrences of an event. The comparator is to determine whether the event count has reached a threshold value. The virtualization control logic is to transfer control of the apparatus from a guest to a host in response to the comparator determining that the event count has reached the threshold value.

US Patent:

20140053155, Feb 20, 2014

Filed:

Oct 23, 2013

Appl. No.:

14/060947

Inventors:

Erik C. Cota-Robles - Mountain View CA, US
Gilbert Neiger - Portland OR, US
Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Forest Grove OR, US

International Classification:

G06F 9/455

US Classification:

718 1

Abstract:

Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is to store a counter enable indicator. The counter enable logic is to enable the counter based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to the guest.

US Patent:

20140076136, Mar 20, 2014

Filed:

Jan 10, 2013

Appl. No.:

13/738608

Inventors:

LAWRENCE LIVERMORE NATIONAL SECURITY, LLC - , US
Andrew T. ANDERSON - Livermore CA, US

Assignee:

LAWRENCE LIVERMORE NATIONAL SECURITY, LLC - Livermore CA

International Classification:

F41A 21/30
F41A 21/34
F41A 21/44

US Classification:

89 141, 89 144

Abstract:

A suppressor is disclosed for use with a weapon having a barrel through which a bullet is fired. The suppressor may have an inner portion having a bore extending coaxially there through. The inner portion is adapted to be secured to a distal end of the barrel. A plurality of axial flow segments project radially from the inner portion and form axial flow paths through which expanding propellant gasses discharged from the barrel flow through. The axial flow segments have radially extending wall portions that help to dissipate heat deposited within the suppressor during firing of the weapon.