Andrew R Chan

US Patent:

6426649, Jul 30, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/751440

Inventors:

Robert Fu - Cupertino CA
David D. Eaton - San Jose CA
Kevin K. Yee - San Jose CA
Andrew K. Chan - Palo Alto CA

Assignee:

QuickLogic Corporation - Sunnyvale CA

International Classification:

H03K 738

US Classification:

326 41, 326 40, 326 39, 326 38, 326 86, 327293, 327292

Abstract:

A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

US Patent:

6519753, Feb 11, 2003

Filed:

Nov 30, 1999

Appl. No.:

09/451681

Inventors:

Roger Ang - Fremont CA
Atul Ahuja - Mountain View CA
Mukesh T. Lulla - Fremont CA
Drazen Borkovic - Mountain View CA
Brian D. Small - Portland OR
Charles C. Tralka - San Jose CA
Andrew K. Chan - Palo Alto CA
Kevin K. Yee - San Jose CA

Assignee:

QuickLogic Corporation - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 16

Abstract:

A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i. e. , it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.

US Patent:

6542096, Apr 1, 2003

Filed:

Aug 24, 2001

Appl. No.:

09/939533

Inventors:

Andrew K. Chan - Palo Alto CA
James M. Apland - Gilroy CA
Senani Gunaratna - Campbell CA
SunilKumar G. Mudunuri - San Jose CA

Assignee:

QuickLogic Corporation - Sunnyvale CA

International Classification:

H03M 900

US Classification:

341100, 716 16

Abstract:

In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.

US Patent:

6552410, Apr 22, 2003

Filed:

Aug 29, 2000

Appl. No.:

09/650773

Inventors:

David D. Eaton - San Jose CA
Kevin K. Yee - San Jose CA
E. Thomas Hart - Los Altos Hills CA
Andrew K. Chan - Palo Alto CA
Neal A. Palmer - La Jolla CA
Michael W. Dini - La Jolla CA
James Apland - Gilroy CA

Assignee:

QuickLogic Corporation - Sunnyvale CA

International Classification:

H01L 2200

US Classification:

257530, 257295, 257296, 257297, 257298, 257299, 257529

Abstract:

A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers.

US Patent:

7202908, Apr 10, 2007

Filed:

Nov 25, 2003

Appl. No.:

10/721376

Inventors:

Qinggang Zhou - Campbell CA, US
Clyde H. Nagakura - Los Gatos CA, US
Sheng-Fu Wu - Cupertino CA, US
Andrew K. Chan - Palo Alto CA, US

International Classification:

H04N 7/01
H04N 11/02

US Classification:

348452, 348458

Abstract:

A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

US Patent:

7218355, May 15, 2007

Filed:

Nov 25, 2003

Appl. No.:

10/722340

Inventors:

Qinggang Zhou - Campbell CA, US
Clyde H. Nagakura - Los Gatos CA, US
Sheng-Fu Wu - Cupertino CA, US
Andrew K. Chan - Palo Alto CA, US

International Classification:

H04N 7/01

US Classification:

348452, 348443, 348458

Abstract:

A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

US Patent:

7346876, Mar 18, 2008

Filed:

Sep 17, 2004

Appl. No.:

10/944323

Inventors:

Andrew K. Chan - Palo Alto CA, US
Thomas M. Chan - Saratoga CA, US
Po Weng Chiu - Campbell CA, US

International Classification:

G06F 17/50
G06F 19/00
G06F 11/00
H03K 19/173
H01L 25/00

US Classification:

716 8, 716 16, 326 38, 326 41, 326 47, 700121, 714 3

Abstract:

A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function. I/O terminals that were used to couple to the external FPGA during system development are usable during normal operation to provide system board access to circuitry within the mask-programmable portion.

US Patent:

7402728, Jul 22, 2008

Filed:

Dec 11, 2003

Appl. No.:

10/537963

Inventors:

Andrew Chee-Yuen Chan - Menlo Park CA, US
Qian Gong - Foster City CA, US
Flavius Martin - Hayward CA, US

Assignee:

Genentech, Inc. - South San Francisco CA

International Classification:

A01K 67/033
C12N 15/00

US Classification:

800 13, 800 9, 800 10, 800 21

Abstract:

The present invention generally relates to non-human transgenic animals expressing human cellular markers, including CD20 and/or preferably CD16.