Andrew J Fish

US Patent:

6381693, Apr 30, 2002

Filed:

Dec 31, 1998

Appl. No.:

09/223809

Inventors:

Andrew J. Fish - Olympia WA
William J. Clem - Olympia WA

Assignee:

Intel Corp. - Santa Clara CA

International Classification:

G06F 9445

US Classification:

713 1, 713 2

Abstract:

A system, a method of operating the system and a system firmware. The system includes a processor and a system firmware including a plurality of customized firmware parts, with each firmware part performing system firmware functions required for and customized to only a subset of a plurality of types of processors which are operational when connected to the system, and a processor identification device, coupled to the system, which identifies which subset of the plurality of types of processors is connected to the system and in response to the identification of the type of connected processor, causes a customized firmware part corresponding to the identified types of processor to be executed by the processor.

US Patent:

6401201, Jun 4, 2002

Filed:

Dec 31, 1998

Appl. No.:

09/223808

Inventors:

Andrew J. Fish - Olympia WA
Yan Li - Olympia WA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15177

US Classification:

713 2

Abstract:

The invention is a system, a method of operating the system and a method of customizing a processing system to operate with different input/output (I/O) systems. A system in accordance with the invention includes a processor, an I/O system coupled to the processor and system firmware, including a plurality of parts which each operate to perform system firmware functions required for and customized to only one of a plurality of different I/O systems which are operational when coupled to the processor, and a storage coupled to the processor, for storing identifying information which, when read, causes only one of the parts of the system firmware to be executed by the processor to perform the system firmware function necessary to operate the one of the different I/O systems identified by the identifying information.

US Patent:

6418487, Jul 9, 2002

Filed:

Apr 30, 1999

Appl. No.:

09/302775

Inventors:

Todd A. Schelling - Lafayette OR
Robert A. Branch - Hillsboro OR
Andrew J. Fish - Olympia WA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

710 15, 714 47, 714 57, 714102, 706904

Abstract:

A method for tracking agents across loss of state events is described. After determining the number of terminal agents within a hierarchical agent system, an algorithm forms a first matrix containing data identifying agents within the hierarchical agent system. After a potential loss of state event has occurred, the algorithm forms a second matrix containing data identifying agents within the hierarchical agent system and compares the first matrix to the second matrix. If the matrices are identical, no agent switch occurred during the potential loss of state event. If the matrices are not identical, at least one agent switch occurred during the potential loss of state event.

US Patent:

6601166, Jul 29, 2003

Filed:

Dec 23, 1999

Appl. No.:

09/471792

Inventors:

Mani Ayyar - Cupertino CA
Sham Datta - Hillsboro OR
Andrew Fish - Olympia WA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9445

US Classification:

713 2, 709222

Abstract:

A mechanism is provided for booting a computer system that is capable of implementing different instruction set architectures, through a network. An embodiment of the invention includes a network controller implemented for a first ISA and a processor capable of implementing programs written in a second ISA as well as programs written in the first ISA. Following preliminary boot operations provided through non-volatile system memory, a network boot program provided by the network controller is implemented. The boot program requests the non-volatile system memory for an indication of the operating system to be loaded and generates a boot request for the indicated operating system. When the indicated operating system is written in the second ISA, the boot program loads the OS to a specified location in system memory and sends the processor into a mode suitable for executing the second ISA.

US Patent:

6754828, Jun 22, 2004

Filed:

Jul 13, 1999

Appl. No.:

09/352715

Inventors:

Suresh Marisetty - San Jose CA
Andrew J. Fish - Olympia WA
Yan Li - Olympia WA
Mani Ayyar - Cupertino CA
Amy ODonnell - Chandler AZ
George Thangadurai - Santa Clara CA
Sham M. Datta - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 942

US Classification:

713200, 713 1, 713 2, 713187, 713201, 710 22, 709310

Abstract:

A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e. g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine.

US Patent:

6928548, Aug 9, 2005

Filed:

Sep 29, 2000

Appl. No.:

09/675113

Inventors:

Robert P. Hale - Portland OR, US
Andrew J. Fish - Olympia WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F011/30
G06F012/14

US Classification:

713187

Abstract:

In one embodiment, a digitally signed image is embodied in a memory component such as a non-volatile memory. The digitally signed image comprises a post-relocation image and a digital signature. The post-relocation image is an image of a software module altered by a symmetrical relocation function by loading of the image into the memory component. The digital signature is based on the image so that it can be used to analyze data integrity.

US Patent:

6961848, Nov 1, 2005

Filed:

Dec 11, 2001

Appl. No.:

10/016055

Inventors:

Andrew J. Fish - Olympia WA, US
Michael D. Kinney - Olympia WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F009/00
G06F009/24
G06F009/445

US Classification:

713 2

Abstract:

An alternative boot methodology that begins with legacy-free firmware allows the peaceful coexistence of legacy-free and legacy option ROMs in a system. Legacy-free firmware provides a legacy-free boot path from system power up to operating system loading. This legacy-free boot path is independent of any legacy firmware. A legacy-free boot manager boots from an ordered list of OS loaders. If a legacy boot option is available, legacy-free drivers that have already been loaded may be stopped, and a legacy boot using legacy firmware may be initiated, without having to reboot the system.

US Patent:

7117396, Oct 3, 2006

Filed:

Dec 28, 2001

Appl. No.:

10/029308

Inventors:

Eshwari P. Komarla - Olympia WA, US
Suresh Marisetty - San Jose CA, US
Mani Ayyar - Cupertino CA, US
Andrew J. Fish - Olympia WA, US
Mohan J. Kumar - Aloha OR, US
Shivnandan D. Kaushik - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 45, 714779

Abstract:

A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.