Andrew S Gallagher

US Patent:

8532197, Sep 10, 2013

Filed:

Feb 16, 2010

Appl. No.:

12/706491

Inventors:

Jonathan Joseph Lareau - Haymarket VA, US
Andrew James Gallagher - Haymarket VA, US

Assignee:

The Aerospace Corporation - El Segundo CA

International Classification:

H04N 7/12

US Classification:

37524026, 37524029, 382265, 3482081

Abstract:

A method for detecting a temporally oscillating source in digital video signals includes: using an imaging device to capture a sequence of input images of a scene; generating digital video signals from the sequence of input images; and processing the digital video signals using a recursive Infinite Impulse Response (IIR) filter technique based on a differentiated version of Goertzel's Algorithm to detect a temporally oscillating source in the digital video signals. In various embodiments, the method also includes generating a visual display of the scene including one or more graphical elements at least one of which pertains to a detected temporally oscillating source.

US Patent:

50723634, Dec 10, 1991

Filed:

Dec 22, 1989

Appl. No.:

7/455759

Inventors:

Andrew M. Gallagher - Long Beach NY

Assignee:

Harris Corporation - Melbourne FL

International Classification:

G06F 1314
G06F 1300

US Classification:

395725

Abstract:

A multimode shared resource arbiter circuit is provided by a programmable array logic module programmed to provide round robin arbitration, or round robin/modified priority arbitration between requests for access to a shared resource, such as a data bus, which is normally provided with only priority arbitration between different access requests. The programmable array logic module is programmed to provide a first option for a round robin arbitration system between different bus access requests, and a second option to put one bus request on a priority basis while other bus requests are round robin arbitrated. The programmable array logic module is programmed to provide a multistate counter cyclically driven between multiple count states by a clock, and each count state having associated therewith a particular request for access to the bus, and if a particular request for access to the bus becomes active while the counter is at its associated count state, the active request is granted and passed as an output, and the counter is frozen at the associated count state, and when the active request is released, the counter resumes being cyclically driven between its multiple count states to resume further round robin arbitration between access requests. The arbiter circuit of the present invention is also applicable to other shared resources such as a shared main storage, a shared RAM memory, etc.