Andrew Thomas Greene

US Patent:

20220413836, Dec 29, 2022

Filed:

Aug 26, 2022

Appl. No.:

17/897005

Inventors:

- Redwood City CA, US
Patricio Echague - Redwood City CA, US
Trevor Stuart - San Mateo CA, US
Andrew Greene - East Palo Alto CA, US

International Classification:

G06F 8/65
G06F 17/18
G06F 11/34

Abstract:

A method and apparatus for event attribution during software experimentation is described. The method may include receiving, by a server computer system, a plurality of event tracking messages associated with an end user system, each event tracking message including at least a customer identifier, an end user identifier, and a timestamp. The method may also include storing each event tracking messages with the received customer identifier, end user identifier, and timestamp in a customer data store. Furthermore, the method may include applying, by the server computer system, a feature treatment to a configurable application executing on the end user system, the feature treatment specified by a customer system associated with the customer identifier, and the feature treatment configures one or more features of the configurable application associated with the end user identifier. The method may also include attributing a first set of events from the received plurality of event tracking messages with the application of the feature treatment.

US Patent:

20220367626, Nov 17, 2022

Filed:

Jul 11, 2022

Appl. No.:

17/861960

Inventors:

- Armonk NY, US
Veeraraghavan S. Basker - Fremont CA, US
Andrew M. Greene - Slingerlands NY, US
Pietro Montanini - Albany NY, US

International Classification:

H01L 29/06
H01L 21/02
H01L 29/78
H01L 29/66

Abstract:

A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.

US Patent:

20210160221, May 27, 2021

Filed:

Nov 26, 2019

Appl. No.:

16/695636

Inventors:

- San Jose CA, US
Ruchi Rajiv Deshpande - Belmont CA, US
Randy Lee Swineford - Sunnyvale CA, US
Nargol Rezvani - Sunnyvale CA, US
Andrew Marc Greene - Newton MA, US
Shawn Alan Gaither - Raleigh NC, US
Michael Kraley - Lexington MA, US

Assignee:

Adobe Inc. - San Jose CA

International Classification:

H04L 29/06
G06N 20/00
G06N 5/04
G06Q 30/02

Abstract:

Systems and techniques for privacy preserving document analysis are described that derive insights pertaining to a digital document without communication of the content of the digital document. To do so, the privacy preserving document analysis techniques described herein capture visual or contextual features of the digital document and creates a stamp representation that represents these features without included the content of the digital document. The stamp representation is projected into a stamp embedding space based on a stamp encoding model generated through machine learning techniques capturing feature patterns and interaction in the stamp representations. The stamp encoding model exploits these feature interactions to define similarity of source documents based on location within the stamp embedding space. Accordingly, the techniques described herein can determine a similarity of documents without having access to the documents themselves.

US Patent:

20200243648, Jul 30, 2020

Filed:

Feb 21, 2020

Appl. No.:

16/798240

Inventors:

- San Jose CA, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US
Jeffrey Shearer - Albany NY, US
Nicole A. Saulnier - Albany NY, US

Assignee:

TESSERA, INC. - San Jose CA

International Classification:

H01L 29/10
H01L 21/8234
H01L 21/8238
H01L 29/66
H01L 27/088
H01L 29/78
H01L 27/092
H01L 21/02
H01L 25/065
H01L 29/417

Abstract:

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

US Patent:

20200044051, Feb 6, 2020

Filed:

Oct 11, 2019

Appl. No.:

16/599164

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US

International Classification:

H01L 29/66
H01L 21/768
H01L 21/027
H01L 27/088
H01L 21/306
H01L 21/8234
H01L 21/8238
H01L 29/78
H01L 21/308
H01L 21/762

Abstract:

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

US Patent:

20200044052, Feb 6, 2020

Filed:

Oct 11, 2019

Appl. No.:

16/599229

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US

International Classification:

H01L 29/66
H01L 21/768
H01L 21/027
H01L 27/088
H01L 21/306
H01L 21/8234
H01L 21/8238
H01L 29/78
H01L 21/308
H01L 21/762

Abstract:

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

US Patent:

20190371912, Dec 5, 2019

Filed:

May 29, 2018

Appl. No.:

15/991128

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US

International Classification:

H01L 29/66
H01L 21/762
H01L 21/308
H01L 21/306
H01L 21/027
H01L 21/8234
H01L 27/088
H01L 21/768
H01L 29/78

Abstract:

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

US Patent:

20190220466, Jul 18, 2019

Filed:

Mar 20, 2019

Appl. No.:

16/359398

Inventors:

- Palo Alto CA, US
Alexander Landau - Palo Alto CA, US
Andrew Greene - Palo Alto CA, US
Brian Dorne - San Francisco CA, US
Bryan Offutt - Palo Alto CA, US
Ernest Zeidman - Palo Alto CA, US
John Garrod - San Mateo CA, US
Katherine Brainard - East Orange NJ, US
Kolin Purcell - San Francisco CA, US
Michael Levin - Bethesda MD, US
Simon Swanson - San Francisco CA, US
Spencer Stecko - Palo Alto CA, US

International Classification:

G06F 16/27
G06F 7/02

Abstract:

Systems and methods are provided for storing a first data object comprising a first set of immutable components, the first data object being associated with a corresponding second data object stored by a remote replication system. A difference is determined between the first set of immutable components of the first data object and a second set of immutable components of the corresponding second data object. A subset of immutable components is identified from the first set of immutable components based on the difference. The subset of immutable components from the first set of immutable components is provided to the remote replication system over a communication network.