Andrew S Mills

US Patent:

6359893, Mar 19, 2002

Filed:

Jul 29, 1999

Appl. No.:

09/363784

Inventors:

Andrew Mills - Coto de Caza CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

H04L 12413

US Classification:

370402, 370463, 370465

Abstract:

A multi-communication rate switching physical device for a port of a mixed communication rate Ethernet repeater network. The present invention includes a physical device for recovering bits from a wire connection (e. g. , fiber, twisted pair, etc. ) that is coupled to computer system adapter. The physical device can be implemented on a single chip integrated within an Ethernet repeater hub within each hub port. The physical device chip of the invention includes a front end multiplexer coupled to channel information between a 10 Base T physical device circuit and a 100 Base T physical device circuit, depending on the result of an auto-negotiation circuit also on the physical device chip. The physical device chip also advantageously employs a second, back end multiplexer, that is coupled to channel data between either the 10 Base T physical device circuit or the 100 Base T physical device circuit and one of a multiple of media independent interfaces (MIIs). The back end multiplexer is controlled by a combination of signals including the auto-negotiation circuit result and a system management interface override signal. By providing multiple MII (or giga MII) interface connections, the invention provides a low cost solution to allow the associated port to be automatically associated with a number of different collision domains within the Ethernet network.

US Patent:

6795450, Sep 21, 2004

Filed:

Sep 28, 2000

Appl. No.:

09/676040

Inventors:

Andrew Mills - Coto De Caza CA
Ralph Andersson - Grass Valley CA

Assignee:

TDK Semiconductor Corporation - Tustin CA

International Classification:

H04L 1266

US Classification:

370463, 370419, 370503, 713300

Abstract:

A link-suspend operation between network nodes in a point-to-point data communications link is presented. Individual network links will have a full power operational mode for supporting full high-bandwidth communication, and a low power âlink-suspendâ (LS) operational mode for temporary operation when only limited communication is occurring. The communications link is maintained, while cycling transmitter power on and off during idle periods with a duty cycle that substantially reduces physical layer device (PHY) power, using LSPs. LS mode may be negotiated by advertising capabilities between two network devices. Thus, PHYs at either end of a link can notify the other of the capability to support a LS mode of operation and can negotiate parameters for communications using the LS mode. Further, transmitting and receiving continuous idles, valid data frames, and Wake-on LAN (WOL) packets is supported. Similarly, notification of âwake-upâ schemes and detection of suspended WOL network device is supported.

US Patent:

7292597, Nov 6, 2007

Filed:

Oct 2, 2002

Appl. No.:

10/263365

Inventors:

Andrew Mills - Coto de Caza CA, US
Ralph Andersson - Nevada City CA, US
Anthony Worsham - Oakmont PA, US
Michael Nootbaar - Nevada City CA, US
David Rosky - Nevada City CA, US
Michael Behrin - Nevada City CA, US

Assignee:

Teridian Semiconductor Corp. - Irvine CA

International Classification:

H04J 3/02

US Classification:

370433, 370459

Abstract:

A method and apparatus for transparent implementation of link-suspend capabilities in network devices is presented, which is capable of operating in full or substantially full power operational mode, as well as in a low power “link-suspend” operational mode. The low power “link-suspend” (LS) mode reduces the power consumption of a LAN communications link at the physical layer by eliminating the need to transmit continuous standard idles to maintain link between two linked partners. In the LS mode, a low duty cycle “link-suspend-packet” (LSP) is transmitted between periods of silent line state (SLS). During the SLS, which is a non-data transmission period, the transmitter may be turned off to conserve power. The transmitter power is turned back on when it is time to transmit LSPs or data.

US Patent:

7317691, Jan 8, 2008

Filed:

Oct 2, 2002

Appl. No.:

10/263464

Inventors:

Andrew Mills - Coto de Caza CA, US
Ralph Andersson - Nevada City CA, US
Anthony Worsham - Oakmont PA, US
Michael Nootbaar - Nevada City CA, US
David Rosky - Nevada City CA, US
Michael Behrin - Nevada City CA, US

Assignee:

Teridian Semiconductor, Corp. - Irvine CA

International Classification:

H04L 12/26

US Classification:

370252, 370250

Abstract:

The invention provides a method for initializing a link suspend device for optimum receive recovery. A method for negotiating link parameters to facilitate rapid recovery of the input data from a silent line state is described. The invention can be applied to network devices in point-to-point data communications links capable of operating in a low power link suspend mode.

US Patent:

7317732, Jan 8, 2008

Filed:

Oct 2, 2002

Appl. No.:

10/263465

Inventors:

Andrew Mills - Coto de Caza CA, US
Ralph Andersson - Nevada City NV, US
Anthony Worsham - Pittsburgh PA, US
Michael Nootbaar - Sun City CA, US
David Rosky - Nevada City NV, US
Michael Behrin - Nevada City NV, US

Assignee:

Teridian Semiconductor, Corp. - Irvine CA

International Classification:

H04L 12/413
H04L 12/26
G06F 1/00

US Classification:

370445, 370463, 370465, 370509, 713320

Abstract:

A method and apparatus for handling data during link suspend pulse and the silent line state of a network device operating in a low power link suspend mode is presented. Accordingly, a new generation of network devices capable of operating in both the full power operational mode of prior art network devices, and a low power “link-suspend” operational mode are presented. The low power “link-suspend” (LS) mode reduces the power consumption of a LAN communications link at the physical layer by eliminating the need to continuously transmit standard idles to maintain link between two linked partners. In the LS mode, a low duty cycle “link-suspend-packet” (LSP) is transmitted between periods of silent line state (SLS). During the SLS, which is a non-data transmission period, the transmitter may be turned off to conserve power therefore preventing the receiver from immediately knowing the phase of an incoming data. Thus, in order to prevent loss of data, the LSPs serve to maintain link and provide information necessary to train the receiver loops so that they can quickly lock onto the incoming data.

US Patent:

7327754, Feb 5, 2008

Filed:

Oct 2, 2002

Appl. No.:

10/263461

Inventors:

Andrew Mills - Coto de Caza CA, US
Ralph Andersson - Nevada City NV, US
Anthony Worsham - Pittsburgh PA, US
Michael Nootbaar - Sun City CA, US
David Rosky - Nevada City CA, US
Michael Behrin - Nevada City CA, US

Assignee:

Teridian Semiconductor, Corp. - Irvine CA

International Classification:

H04L 12/66

US Classification:

370463, 370419, 370503, 709250, 713320

Abstract:

A method for maintaining the states of a receiver during the silent line state of a network device operating in a low power link suspend mode is presented. Accordingly, a method of freezing the states of the equalizer and keeping the receiver clock locked to a frequency that is approximately equal to that of the input data while providing for rapid adjustment to the phase and thus recovery of the input data is presented. During Silent Line State (SLS), the receiver states are frozen using methods that avoid parasitic decay. Also, the receive clock phase lock loop is locked onto the local transmit clock since the local transmit clock has a frequency approximating the incoming data frequency. During the SLS, the transmitter of the remote network device may have been turned off to conserve power therefore the receiver has no way of immediately knowing the phase of an incoming data. Thus, in order to prevent loss of data, the receiver loops of the receiving network device are trained to the frequency of the transmitting remote network device using periodic Link Suspend packets.

US Patent:

20120110259, May 3, 2012

Filed:

Oct 26, 2011

Appl. No.:

13/282411

Inventors:

Andrew Mills - Coto de Caza CA, US
Marshall Lee - Newport Coast CA, US

Assignee:

ENMOTUS INC. - Aliso Viejo CA

International Classification:

G06F 12/08
G06F 12/06

US Classification:

711113, 711209, 711E12017, 711E12078

Abstract:

A method of operation of a data storage system includes: enabling a system interface for receiving host commands; updating a mapping register for monitoring transaction records of a logical block address for the host commands including translating a host virtual block address to a physical address for storage devices; accessing by a storage processor, the mapping register for comparing the transaction records with a tiering policies register; and enabling a tiered storage engine for transferring host data blocks by the system interface and concurrently transferring between a tier zero, a tier one, or a tier two if the storage processor determines the transaction records exceed the tiering policies register.

US Patent:

59913037, Nov 23, 1999

Filed:

Jul 28, 1997

Appl. No.:

8/901112

Inventors:

Andrew Mills - Coto de Caza CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

H04L 12413

US Classification:

370402

Abstract:

A multi-communication rate switching physical device for a port of a mixed communication rate Ethernet repeater network. The present invention includes a physical device for recovering bits from a wire connection (e. g. , fiber, twisted pair, etc. ) that is coupled to computer system adapter. The physical device can be implemented on a single chip integrated within an Ethernet repeater hub within each hub port. The physical device chip of the invention includes a front end multiplexer coupled to channel information between a 10 Base T physical device circuit and a 100 Base T physical device circuit, depending on the result of an auto-negotiation circuit also on the physical device chip. The physical device chip also advantageously employs a second, back end multiplexer, that is coupled to channel data between either the 10 Base T physical device circuit or the 100 Base T physical device circuit and one of a multiple of media independent interfaces (MIIs). The back end multiplexer is controlled by a combination of signals including the auto-negotiation circuit result and a system management interface override signal.