Andrew D Petersen

US Patent:

20060179429, Aug 10, 2006

Filed:

Nov 22, 2005

Appl. No.:

11/284760

Inventors:

Susan Eggers - Seattle WA, US
Martha Mercaldi - Seattle WA, US
Kenneth Michelson - New York NY, US
Mark Oskin - Seattle WA, US
Andrew Petersen - Seattle WA, US
Andrew Putnam - Seattle WA, US
Andrew Schwerin - Seattle WA, US
Steven Swanson - Seattle WA, US

Assignee:

University of Washington - Seattle WA

International Classification:

G06F 9/45

US Classification:

717151000

Abstract:

A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.

US Patent:

20070271556, Nov 22, 2007

Filed:

Jul 30, 2007

Appl. No.:

11/830446

Inventors:

Susan Eggers - Seattle WA, US
Martha Mercaldi - Seattle WA, US
Kenneth Michelson - New York NY, US
Mark Oskin - Seattle WA, US
Andrew Petersen - Seattle WA, US
Andrew Putnam - Seattle WA, US
Andrew Schwerin - Seattle WA, US
Steven Swanson - Seattle WA, US

Assignee:

University of Washington - Seattle WA

International Classification:

G06F 9/45

US Classification:

717151000

Abstract:

A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.