Andy J Chan

US Patent:

6462591, Oct 8, 2002

Filed:

Jun 14, 2001

Appl. No.:

09/882420

Inventors:

John B. Dillon - late of Palo Alto CA
by Nancy David Dillon - Marshall VA
Michael Tak-Kei Ching - Sunnyvale CA
William F. Stonecypher - San Jose CA
Andy Peng-Pui Chan - San Jose CA
Matthew M. Griffin - Mountain View CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H03B 100

US Classification:

327112

Abstract:

A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.

US Patent:

6870419, Mar 22, 2005

Filed:

Jul 23, 2003

Appl. No.:

10/625264

Inventors:

Nancy David Dillon - Marshall VA, US
Michael Tak-Kei Ching - Sunnyvale CA, US
William F. Stonecypher - San Jose CA, US
Andy Peng-Pui Chan - San Jose CA, US
Matthew M. Griffin - Mountain View CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G05F001/10

US Classification:

327535

Abstract:

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (), an analog voltage divider (), an input comparator (), a sampling latch (), a current control counter (), and a bitwise output driver (output driver A and output driver B ).