Andy Chen

US Patent:

59299240, Jul 27, 1999

Filed:

Mar 10, 1997

Appl. No.:

8/815401

Inventors:

Andy His-Wen Chen - San Jose CA

Assignee:

NeoMagic Corp. - Santa Clara CA

International Classification:

H04N 700

US Classification:

348552

Abstract:

A scan converter receives VGA or SVGA graphics data and outputs NTSC or PAL TV data. The scan converter is integrated inside a personal computer's graphics controller, allowing the digital-to-analog converter (DAC) to be used for either CRT-pixel conversion or TV encoding. The VGA timing is altered to better match with TV scan-conversion. The horizontal rate is not constant but can be increased or decreased during the vertical blanking period. A second register is provided for the total number of pixels in a line during vertical blanking, while a first register contains the total number of pixels in a displayable line not during the vertical blanking period. Since lines with fewer pixels require less time to display, the period of time or rate for blanked lines is changed. An extra horizontal line is added during vertical blanking for every second frame for SVGA conversion to better match the asymmetry of TV standards. While CRT's cannot accept the variable line rate, flat-panel displays can operate properly even when the horizontal rate varies.

US Patent:

20220180903, Jun 9, 2022

Filed:

Feb 23, 2022

Appl. No.:

17/678367

Inventors:

Zuoliang Chen - San Francisco CA, US
Anissa Chen - San Francisco CA, US
Andy Chen - San Francisco CA, US

International Classification:

G11B 27/036
H04N 5/92
H04N 5/232
H04N 5/265
G06Q 30/02

Abstract:

The system and method of duet video creating and advertising of the present invention is a digital platform that provides duet templates for video creators to create duet videos, each duet template is associated with a right template clip selection button, a left template clip selection button, an invitation button and a sponsor button, such that a creator can use the right or left template clip selection button to choose to act as the right or left template clip, use the invitation button to invite someone to create a duet video together, and an advertiser can use the sponsor button to sponsor a template and embed ad to the template, such that a duet video created from a duet template will carry the same embedded ad, and the embedded ad can be shared together with the duet video to other video or social platforms. In a preferred embodiment, the system of the present invention comprising at least one digital device, a duet video app and a database, the duet video app further composing a template displaying module, a duet clip creating module, a duet video creating module, an invitation duet video creating module, a sponsor ad embedding module, a template creating module, a template uploading module, and a duet video sharing module. The present invention gives duet video creators the option. to watch a demo, choose a role, react to a counterpart, and select someone to duet with, and it provides a method for advertisers to use duet videos to promote their brands, products or service at a cost effective way.

US Patent:

20210111702, Apr 15, 2021

Filed:

Oct 15, 2020

Appl. No.:

17/071849

Inventors:

- Torrance CA, US
Liping D. Hou - Torrance CA, US
Kun-Mao Pan - Harbor City CA, US
Andy Chien-Hsiang Chen - Cypress CA, US
Robert B. Stokes - Rancho Palos Verdes CA, US

International Classification:

H03H 9/17
H03H 9/02
H03H 9/13

Abstract:

A bulk acoustic wave (BAW) resonator includes a substrate, a stack over the substrate and including a piezoelectric layer disposed between two electrode layers, and one or more edge frames. The one or more edge frames can be a raised metal frame extending parallel to a periphery of an active region of the stack and has one or more slanted cuts such that the edge frame does not form a closed loop and loss of acoustic energy in the active region through the one or more cuts is reduced, minimized or prevented. Alternatively or additionally, the one or more edge frames include a recessed edge frame in the form of a trench in the piezoelectric layer extending parallel to a boundary of the active region, and may further include a second edge frame formed on the first electrode and embedded in the piezoelectric layer.

US Patent:

20200336394, Oct 22, 2020

Filed:

Jun 8, 2020

Appl. No.:

16/895621

Inventors:

- Palo Alto CA, US
Andrew Ash - San Carlos CA, US
Anuraag Bahl - New York NY, US
Andy Chen - New York NY, US
Aydin Keskin - Jersey City NJ, US
Christopher Rogers - Brooklyn NY, US
Anshuman Prasad - New York NY, US
Ankit Shankar - Redwood City CA, US
Casey Patton - London, GB
Christopher Wynnyk - Washington DC, US
Joanna Peller - London, GB
Jonathan Victor - New York NY, US
Mackenzie Bohannon - San Rafael CA, US
Mitchell Skiles - New York NY, US
Nikhil Taneja - New York NY, US
Ryan Norris - London, GB
Scott Adams - London, GB
Samuel Sinensky - New York NY, US
Sri Krishna Vempati - Santa Clara CA, US
Thomas Mathew - New York NY, US
Vinoo Ganesh - New York NY, US
Rahij Ramsharan - London, GB

International Classification:

H04L 12/24
G06K 9/62

Abstract:

A system for troubleshooting network problems is disclosed. A model can use demographic information, network usage information, and network membership information to determine an importance of a problem. The importance of the problem for the user who reported the problem, a number of other users affected by the problem, and the importance of the problem to the other users can be used to determine a priority for resolving the problem. Before and after a work order is executed to resolve the problem, network metrics can be gathered, including aggregate network metrics, and automatically presented in various user interfaces. The analysis of the metrics can be used to update a database of which work orders are assigned in response to which problems.

US Patent:

20190026417, Jan 24, 2019

Filed:

Sep 24, 2018

Appl. No.:

16/140461

Inventors:

- Cambridge, GB
Jerry Chaoyuan Wang - Fremont CA, US
Brian Tracy Cline - Austin TX, US
Xiaoqing Xu - Austin TX, US
Andy Wangkun Chen - Austin TX, US
Yew Keong Chong - Austin TX, US
Tom Shore - Austin TX, US
Sriram Thyagarajan - Austin TX, US
Gus Yeung - Austin TX, US
Daniel J. Albers - Beaver PA, US
David William Granda - Austin TX, US

International Classification:

G06F 17/50

Abstract:

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

US Patent:

20180331681, Nov 15, 2018

Filed:

Jul 23, 2018

Appl. No.:

16/042949

Inventors:

- Cambridge, GB
Vivek Nautiyal - Milpitas CA, US
Andy Wangkun Chen - Austin TX, US
Jitendra Dasani - Cupertino CA, US
Bo Zheng - Cupertino CA, US
Akshay Kumar - New Delhi, IN
Vivek Asthana - Greater Noida, IN

International Classification:

H03K 17/22
G11C 5/14

Abstract:

Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

US Patent:

20180225402, Aug 9, 2018

Filed:

Oct 30, 2014

Appl. No.:

14/528314

Inventors:

- Cambridge, GB
Jerry Chaoyuan Wang - Fremont CA, US
Brian Douglas Ngai Lee - Oakland, CA
Brian Tracy Cline - Austin TX, US
Xiaoqing Xu - Austin TX, US
Andy Wangkun Chen - Austin TX, US
Yew Keong Chong - Austin TX, US
Tom Shore - Austin TX, US
Sriram Thyagarajan - Austin TX, US
Gus Yeung - Austin TX, US
Yanbin Jiang - Fremont CA, US
Emmanuel Jean Marie Olivier Pacaud - St. Joseph de Riviere, FR
Matthieu Domonique Henri Pauly - Grenoble, FR
Sylvia Xiuhui Li - Sunnyvale CA, US
Thanusree Achuthan - Great Cambourne, GB
Daniel J. Albers - Beaver PA, US
David William Granda - Austin TX, US

International Classification:

G06F 17/50

Abstract:

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

US Patent:

20170317672, Nov 2, 2017

Filed:

Apr 29, 2016

Appl. No.:

15/143197

Inventors:

- Cambridge, GB
Vivek Nautiyal - Milpitas CA, US
Andy Wangkun Chen - Austin TX, US
Jitendra Dasani - Cupertino CA, US
Bo Zheng - Cupertino CA, US
Akshay Kumar - New Delhi, IN
Vivek Asthana - Greater Noide, IN

International Classification:

H03K 17/22
G11C 5/14

Abstract:

Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.