Andy Nguyen Tran

US Patent:

20190295935, Sep 26, 2019

Filed:

May 30, 2019

Appl. No.:

16/427172

Inventors:

- Dallas `T, US
Alok Kumar Lohia - Dallas TX, US
Andy Quang Tran - Grand Prairie TX, US

International Classification:

H01L 23/495
H01L 23/00
H01L 21/48
H01L 23/367
H01L 23/29

Abstract:

A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals.A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

US Patent:

20180277465, Sep 27, 2018

Filed:

Mar 23, 2018

Appl. No.:

15/934516

Inventors:

- Dallas TX, US
Andy Quang Tran - Grand Prairie TX, US

International Classification:

H01L 23/495
H01L 21/48
H01L 23/31

Abstract:

A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.

US Patent:

20170162489, Jun 8, 2017

Filed:

Feb 21, 2017

Appl. No.:

15/438533

Inventors:

- DALLAS TX, US
Alok Kumar Lohia - Dallas TX, US
Andy Quang Tran - Grand Prairie TX, US

International Classification:

H01L 23/495

Abstract:

A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the hack side of the terminals each include a contact region which lacks the plating layer.

US Patent:

20170062315, Mar 2, 2017

Filed:

May 24, 2016

Appl. No.:

15/162807

Inventors:

- Dallas TX, US
ALOK KUMAR LOHIA - DALLAS TX, US
ANDY QUANG TRAN - GRAND PRAIRIE TX, US

International Classification:

H01L 23/495
H01L 23/367
H01L 23/29
H01L 23/00

Abstract:

A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

US Patent:

20160286652, Sep 29, 2016

Filed:

Mar 27, 2015

Appl. No.:

14/671727

Inventors:

- Dallas TX, US
Alok Kumar Lohia - Dallas TX, US
Andy Quang Tran - Grand Prairie TX, US

International Classification:

H05K 1/18
G06T 7/00
H04N 7/18
H05K 3/30

Abstract:

An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.