Andy W Yu

US Patent:

7276759, Oct 2, 2007

Filed:

Mar 11, 2004

Appl. No.:

10/798138

Inventors:

Andy Yu - Palo Alto CA, US
Ying W. Go - Palo Alto CA, US

Assignee:

Nanostar Corporation - Palo Alto CA

International Classification:

H01L 29/788

US Classification:

257317, 438267, 257E21179

Abstract:

In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.

US Patent:

7449744, Nov 11, 2008

Filed:

Aug 3, 2004

Appl. No.:

10/910198

Inventors:

Andy Yu - Palo Alto CA, US
Ying W. Go - Palo Alto CA, US

Assignee:

Nanostar Corporation - San Jose CA

International Classification:

H01L 23/62
H01L 29/93

US Classification:

257316, 257318, 257319, 257550, 438293

Abstract:

A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.

US Patent:

7544566, Jun 9, 2009

Filed:

May 4, 2007

Appl. No.:

11/744730

Inventors:

Andy T. Yu - Palo Alto CA, US
Ying W. Go - Palo Alto CA, US

Assignee:

Nanostar Corporation - Palo Alto CA

International Classification:

H01L 21/336

US Classification:

438257, 257E2168

Abstract:

A self-aligned method for manufacturing an electrically alterable memory device on a semiconductor layer includes (a) forming an insulating layer on the semiconductor layer, (b) depositing a first conductive layer on the insulating layer, (c) forming trench isolation regions along and into the semiconductor layer, (d) depositing a sacrificial material on the first conductive layer, (e) etching the sacrificial material to form isolation channels, (f) forming two gate masks along lateral sides of the sacrificial material, (g) etching the first conductive layer to extend the channels to the insulating layer, (h) etching the sacrificial material to form a control channel, (i) etching the block of the first conductive layer, and (j) filling the control channel with a second conductive layer.

US Patent:

7834388, Nov 16, 2010

Filed:

Feb 6, 2006

Appl. No.:

11/348556

Inventors:

Andy Yu - Palo Alto CA, US
Ying W. Go - Palo Alto CA, US

Assignee:

Nanostar Corporation - Palo Alto CA

International Classification:

H01L 29/788
H01L 21/8238

US Classification:

257316, 257208, 257E27103, 257E29304, 257E29308, 36518506, 36518512

Abstract:

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

US Patent:

20060081910, Apr 20, 2006

Filed:

Dec 2, 2005

Appl. No.:

11/292922

Inventors:

Andy Yu - Palo Alto CA, US
Ying Go - Palo Alto CA, US

International Classification:

H01L 29/788

US Classification:

257315000

Abstract:

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

US Patent:

20060113585, Jun 1, 2006

Filed:

Jan 12, 2006

Appl. No.:

11/330887

Inventors:

Andy Yu - Palo Alto CA, US
Ying Go - Palo Alto CA, US

International Classification:

H01L 29/788

US Classification:

257316000

Abstract:

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

US Patent:

20060157773, Jul 20, 2006

Filed:

Jan 14, 2005

Appl. No.:

11/036911

Inventors:

Andy Yu - Palo Alto CA, US
Ying Go - Palo Alto CA, US

International Classification:

H01L 29/76

US Classification:

257314000

Abstract:

A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.

US Patent:

20070297246, Dec 27, 2007

Filed:

Sep 7, 2007

Appl. No.:

11/851913

Inventors:

Andy Yu - Palo Alto CA, US
Ying Go - Palo Alto CA, US

International Classification:

G11C 16/04
H01L 29/788

US Classification:

365185280, 257321000, 257E29304

Abstract:

In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.