Aniket R Kadkol from 19876 Beekman Pl, Cupertino, CA 95014, age 45

Aniket Kadkol Phones & Addresses

19876 Beekman Pl, Cupertino, CA 95014
Sunnyvale, CA
New York, NY
Mountain View, CA
Placentia, CA
Burbank, CA
Los Angeles, CA
Medford, NY
Hauppauge, NY
Fremont, CA
Santa Monica, CA
395 Ano Nuevo Ave APT 809, Sunnyvale, CA 94085

Work

Company:

Appliedmicro/macom
Jan 2017
Position:

High speed io and serdes design

Education

Degree:

Master of Science, Masters
School / High School:

University of Southern California

Skills

Mixed Signal • Analog • Serdes • Verilog • Asic • Semiconductors • Soc • Rtl Design • Pll • Electrical Engineering • Fpga • Cmos • Ic • System on A Chip • Application Specific Integrated Circuits

Ranks

Certificate:

Machine Learning

Industries

Semiconductors

Resumes

High Speed Io And Serdes Design

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Location:

1320 Ridder Park Dr, San Jose, CA 95131

Industry:

Semiconductors

Work:

Appliedmicro/Macom
High Speed Io and Serdes Design
Broadcom Feb 2016 - Jan 2017
Serdes Design
Lsi Corporation Jul 2011 - Feb 2016
Serdes Design
Altera Dec 2005 - Jun 2011
Senior Design Engineer

Education:

University of Southern California
Master of Science, Masters

Skills:

Mixed Signal
Analog
Serdes
Verilog
Asic
Semiconductors
Soc
Rtl Design
Pll
Electrical Engineering
Fpga
Cmos
Ic
System on A Chip
Application Specific Integrated Circuits

Certifications:

Machine Learning
Introduction To Marketing

Us Patents

Scaleable Look-Up Table Based Memory
view source
US Patent:

8644100, Feb 4, 2014
Filed:

Oct 20, 2011
Appl. No.:

13/277871
Inventors:

Philip Pan - Fremont CA, US
Andy L. Lee - San Jose CA, US
Lu Zhou - Santa Clara CA, US
Aniket Kadkol - Mountain View CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

G11C 7/00
US Classification:

365203, 365226, 365227, 365228, 365229
Abstract:

An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Scaleable Look-Up Table Based Memory
view source
US Patent:

8064280, Nov 22, 2011
Filed:

Jun 10, 2008
Appl. No.:

12/136201
Inventors:

Philip Pan - Fremont CA, US
Andy L. Lee - San Jose CA, US
Lu Zhou - Santa Clara CA, US
Aniket Kadkol - Mountain View CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

G11C 5/14
US Classification:

365226, 365191, 36518509, 36518513
Abstract:

An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Aniket R Kadkol