Anil K Gupta

US Patent:

6594183, Jul 15, 2003

Filed:

Jun 30, 1998

Appl. No.:

09/108084

Inventors:

Karl M. J. Lofgren - Newport Beach CA
Robert D. Norman - San Jose CA
Gregory B. Thelin - Garden Grove CA
Anil Gupta - Irvine CA

Assignee:

SanDisk Corporation - Sunnyvale CA
Western Digital Corporation - Irvine CA

International Classification:

G11C 1604

US Classification:

36518533, 36523001, 36523003, 36518529, 36518509

Abstract:

A mass storage system made of flash electrically erasable and programmable read only memory (âEEPROMâ) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

US Patent:

6715044, Mar 30, 2004

Filed:

Aug 22, 2001

Appl. No.:

09/939290

Inventors:

Karl M. J. Lofgren - Newport Beach CA
Jeffrey Donald Stai - Placentia CA
Anil Gupta - Irvine CA
Robert D. Norman - San Jose CA
Sanjay Mehrotra - Milipitas CA

Assignee:

SanDisk Corporation - Sunnyvale CA
Western Digital Corporation - Lake Forest CA

International Classification:

G06F 1200

US Classification:

711154, 711103

Abstract:

A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.

US Patent:

6850443, Feb 1, 2005

Filed:

May 2, 2003

Appl. No.:

10/428422

Inventors:

Karl M. J. Lofgren - Newport Beach CA, US
Robert D. Norman - San Jose CA, US
Gregory B. Thelin - Garden Grove CA, US
Anil Gupta - Irvine CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA
Western Digital Corporation - Lake Forest CA

International Classification:

G11C 1100

US Classification:

36518529, 36518511, 36518533, 365218

Abstract:

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

US Patent:

7353325, Apr 1, 2008

Filed:

Jan 3, 2005

Appl. No.:

11/028882

Inventors:

Karl M. J. Lofgren - Newport Beach CA, US
Robert D. Norman - San Jose CA, US
Gregory B. Thelin - Garden Grove CA, US
Anil Gupta - Irvine CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G06F 12/02

US Classification:

711103, 711154, 3651853, 718105

Abstract:

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

US Patent:

7688643, Mar 30, 2010

Filed:

Mar 24, 2004

Appl. No.:

10/809061

Inventors:

Karl M. J. Lofgren - Newport Beach CA, US
Jeffrey Donald Stai - Placentia CA, US
Anil Gupta - Irvine CA, US
Robert D. Norman - San Jose CA, US
Sanjay Mehrotra - Milpitas CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 16/04
G06F 13/00

US Classification:

36518528, 36518511, 711103, 711154, 711203

Abstract:

A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.

US Patent:

8125834, Feb 28, 2012

Filed:

Nov 16, 2009

Appl. No.:

12/619581

Inventors:

Karl M. J. Lofgren - Newport Beach CA, US
Jeffrey Donald Stai - Placentia CA, US
Anil Gupta - Irvine CA, US
Robert D. Norman - San Jose CA, US
Sanjay Mehrotra - Milpitas CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 16/04
G06F 13/00

US Classification:

36518528, 36518511, 711103, 711154, 711203

Abstract:

A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.

US Patent:

20040168014, Aug 26, 2004

Filed:

Feb 23, 2004

Appl. No.:

10/785373

Inventors:

Karl Lofgren - Newport Beach CA, US
Jeffrey Donald Stai - Placentia CA, US
Anil Gupta - Irvine CA, US
Robert Norman - San Jose CA, US
Sanjay Mehrotra - Milpitas CA, US

International Classification:

G06F012/00

US Classification:

711/103000

Abstract:

A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

US Patent:

20080162798, Jul 3, 2008

Filed:

Feb 27, 2008

Appl. No.:

12/038666

Inventors:

Karl M.J. Lofgren - Newport Beach CA, US
Robert D. Norman - San Jose CA, US
Gregory B. Thelin - Garden Grove CA, US
Anil Gupta - Irvine CA, US

International Classification:

G06F 12/00

US Classification:

711103, 711E12001

Abstract:

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.