Anil X Gupta

US Patent:

6351152, Feb 26, 2002

Filed:

Sep 23, 1999

Appl. No.:

09/401743

Inventors:

Srinivas T. Reddy - Santa Clara CA
Anil Gupta - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 1762

US Classification:

326105, 327408

Abstract:

A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

US Patent:

6359810, Mar 19, 2002

Filed:

Apr 4, 2000

Appl. No.:

09/542434

Inventors:

Anil Gupta - San Jose CA
Steven J. Schumann - Sunnyvale CA

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 1604

US Classification:

36518529, 36518512, 36518518

Abstract:

In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately -10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6. 5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.

US Patent:

6493773, Dec 10, 2002

Filed:

Nov 15, 2000

Appl. No.:

09/713998

Inventors:

Thomas Daniel - Los Altos CA
Anil Gupta - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1314

US Classification:

710 52, 710 53, 710 55, 710 57, 710 33, 710 35, 709213, 709216

Abstract:

To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processors descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

US Patent:

6615296, Sep 2, 2003

Filed:

Jun 14, 2001

Appl. No.:

09/881512

Inventors:

Thomas Daniel - Los Altos CA
Anil Gupta - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1320

US Classification:

710 57, 710 33, 710 34, 710 35, 710 52, 710 53

Abstract:

To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processors descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

US Patent:

7317630, Jan 8, 2008

Filed:

Jul 15, 2005

Appl. No.:

11/182374

Inventors:

Nicola Telecco - San Jose CA, US
Vijay P. Adusumilli - San Jose CA, US
Anil Gupta - Saratoga CA, US
Edward Hui - Cupertino CA, US
Steven J. Schumann - Sunnyvale CA, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 5/06

US Classification:

365 63, 36518901

Abstract:

A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.

US Patent:

7787289, Aug 31, 2010

Filed:

Dec 3, 2007

Appl. No.:

11/949693

Inventors:

Krishnakumar Mani - San Jose CA, US
Jannier Maximo Roiz Wilson - Santa Clara CA, US
Anil Gupta - Saratoga CA, US
Kimihiro Satoh - Santa Clara CA, US

Assignee:

Magsil Corporation - Santa Clara CA

International Classification:

G11C 11/00

US Classification:

365158, 365 66, 365148, 365171, 3652255, 3652435, 977935

Abstract:

Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.

US Patent:

8279897, Oct 2, 2012

Filed:

Mar 2, 2010

Appl. No.:

12/715774

Inventors:

Jung Gun Lee - Palo Alto CA, US
Raul Herman Etkin - San Francisco CA, US
Sung-Ju Lee - San Francisco CA, US
Anil Gupta - Shrewsbury MA, US
Vincent Ma - Shrewsbury MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04J 3/06
H04L 7/00
H04B 15/00

US Classification:

370503, 375356, 455502

Abstract:

A wireless node receives a beacon from a wireless access point. The beacon includes a wireless protocol time synchronization function (TSF) timestamp generated with reference to a global clock for a network. The wireless node synchronizes a counter according to the TSF timestamp. The wireless node receives a global timing offset (GTO) packet from the wireless access point and combines the GTO packet with a counter value to generate a global timestamp.

US Patent:

8400866, Mar 19, 2013

Filed:

Aug 6, 2010

Appl. No.:

12/852335

Inventors:

Krishnakumar Mani - San Jose CA, US
Anil Gupta - Saratoga CA, US

Assignee:

Magsil Corporation - Santa Clara CA

International Classification:

G11C 8/00

US Classification:

36523006, 365171

Abstract:

A current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor (M) to control driver currents from the current driver circuit, and wherein the transistor (M) has a smaller form factor then otherwise possible by virtue of maintaining a gate thereof at a negative voltage.