Anil Lalitkumar Pandya

US Patent:

6427226, Jul 30, 2002

Filed:

May 25, 1999

Appl. No.:

09/318782

Inventors:

Dhiraj Mallick - Sunnyvale CA
Jacob Thomas - San Jose CA
Rajesh Khanna - Fremont CA
Anil L. Pandya - Fremont CA
Satish Kumar Raj - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 10

Abstract:

Tools and techniques used in conjunction with integrated circuit path timing information can selectively reduce the channel length of transistors in cells associated with the most critical paths in an integrated circuit, while keeping the overall integrated circuit design within a specified power budget. Moreover, by targeting pins of cells (and thus their associated transistors) that are used by multiple paths, and/or that offer the greatest potential speed improvement, timing violations along critical paths can be reduced or eliminated with a relatively few number of replacements. Paths within a certain timing violation range are selected for analysis. The pins within those paths are ranked by pin criticality, which can depend on, for example, the number of times a particular pin occurs in any path, the timing enhancement associated with replacing a cell having that pin, and the impact of replacing a cell having that pin would have on the power budget. Transistors within cells (or entire cells) associated with pins are replaced based on the pin criticality until timing improvements are sufficient to remove a path from the range of paths being examined. Successive paths, and ranges of paths are analyzed until the power budget is exceeded, or no more improvements can be made.