Animesh N Mishra

US Patent:

6876593, Apr 5, 2005

Filed:

Jul 1, 2003

Appl. No.:

10/612585

Inventors:

Jun Shi - San Jose CA, US
Animesh Mishra - Milpitas CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C007/00

US Classification:

365222, 365228

Abstract:

Memory devices, refresh logic and approaches to selectively refresh each row of memory cells within a memory device depending on whether or not each is marked as having data to be preserved.

US Patent:

7099735, Aug 29, 2006

Filed:

Jun 30, 2004

Appl. No.:

10/882546

Inventors:

Sandeep K. Jain - Milpitas CA, US
George Vergis - Hillsboro OR, US
Animesh Mishra - Pleasanton CA, US
Jun Shi - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01K 1/00
G01K 1/08
G06F 7/00

US Classification:

700132, 702130, 700299

Abstract:

In one embodiment a memory controller is provided. The memory controller comprises a predictive logic circuit to predict an increase in a current operating temperature of a memory device coupled to the memory controller, based on memory cycles to be issued to the memory device; and a temperature control circuit to perform a temperature control operation wherein if the sum of the current operating temperature and the predicted increase in temperature is greater than a threshold temperature associated with the memory device, then the number of memory cycles issued to the memory device is reduced.

US Patent:

7145823, Dec 5, 2006

Filed:

Jun 30, 2004

Appl. No.:

10/882553

Inventors:

Sandeep K. Jain - Milpitas CA, US
Animesh Mishra - Pleasanton CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/04

US Classification:

365211, 365212

Abstract:

In one embodiment, a method includes periodically charging a capacitor mounted on an electronic component; initializing a timer to count down from a counter value, once the capacitor is charged; determining if the capacitor has discharged before the timer has counted down to zero; and if the capacitor has discharged before the timer has counted down to zero then generating an interrupt.

US Patent:

7197591, Mar 27, 2007

Filed:

Jun 30, 2004

Appl. No.:

10/882544

Inventors:

Seh Kwa - San Jose CA, US
Animesh Mishra - Pleasanton CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26
G06F 13/00
G06F 13/14
H03K 19/0175
G09G 3/00

US Classification:

710307, 713300, 713320, 326 86

Abstract:

A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

US Patent:

7236599, Jun 26, 2007

Filed:

May 22, 2000

Appl. No.:

09/577399

Inventors:

Jun Shi - San Jose CA, US
Animesh Mishra - Milpitas CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04R 5/00
H04R 3/00
H04B 1/00
G06F 17/00

US Classification:

381 22, 381119, 381111, 700 94

Abstract:

A codec in a processor-based system handles at least two separate audio programs at the same time. This may be useful, for example, for simultaneously playing one audio program while recording another audio program. A first digital to analog converter pair may be coupled to a first mixer and a second digital to analog converter pair may include a second mixer. Thus, two separate audio programs may be handled at the same time, each by a separate digital to analog converter and mixer.

US Patent:

7260007, Aug 21, 2007

Filed:

Mar 30, 2005

Appl. No.:

11/093905

Inventors:

Sandeep Jain - Milpitas CA, US
David Wyatt - San Jose CA, US
Jun Shi - San Jose CA, US
Animesh Mishra - Pleasanton CA, US
John Halbert - Beaverton OR, US
Melik Isbara - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 5/06
G11C 7/04
G11C 7/00

US Classification:

365212, 365211, 365227, 365 72, 365 63, 365 51

Abstract:

Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

US Patent:

7304905, Dec 4, 2007

Filed:

May 24, 2004

Appl. No.:

10/852923

Inventors:

Pochang Hsu - Fremont CA, US
Animesh Mishra - Pleasanton CA, US
Jun Shi - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/04

US Classification:

365212, 365211, 36523002, 365233, 365 72, 365 63, 365 51

Abstract:

Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

US Patent:

7342841, Mar 11, 2008

Filed:

Dec 21, 2004

Appl. No.:

11/019881

Inventors:

Sandeep K. Jain - Milpitas CA, US
Animesh Mishra - Pleasanton CA, US
John B. Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365222, 36523003, 711106

Abstract:

A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.