Anna Lang Phillips

US Patent:

6891229, May 10, 2005

Filed:

Apr 30, 2003

Appl. No.:

10/426296

Inventors:

Andrea Franke - Austin TX, US
Jonathan Cobb - Austin TX, US
John M. Grant - Austin TX, US
Al T. Koh - Austin TX, US
Anna M. Phillips - Manchaca TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L027/01
H01L029/00

US Classification:

257354, 257506

Abstract:

A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts () are formed on a substrate () through successive deposition, lithography, and etching steps. The posts comprise a bottom layer () of silicon dioxide and an overlying etch-stop layer of silicon nitride (). An insulating material () is then deposited over the isolation posts and areas of the substrate. Isolation structures () are established by etching the insulating material to form convex sidewall spacers () at the vertical walls of the isolation posts. Active areas () between spacers are filled with semiconductor material. In an embodiment, a strained cap layer () may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.

US Patent:

6924184, Aug 2, 2005

Filed:

Mar 21, 2003

Appl. No.:

10/394352

Inventors:

Nigel G. Cave - Austin TX, US
Anna M. Phillips - Manchaca TX, US
Terry G. Sparks - Montbonnot St. Martin, FR

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L021/8238

US Classification:

438201, 438211

Abstract:

Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

US Patent:

20040102040, May 27, 2004

Filed:

Nov 22, 2002

Appl. No.:

10/301993

Inventors:

Olubunmi Adetutu - Austin TX, US
Marc Rossow - Austin TX, US
Anna Phillips - Manchaca TX, US

International Classification:

H01L021/31
H01L021/44
H01L021/469

US Classification:

438/680000, 438/785000, 438/786000, 438/787000, 438/791000

Abstract:

Heating a reaction chamber or other apparatus in the absence of product wafers to a “curing” temperature above a deposition temperature between the deposition of a film on a first set of semiconductor product wafers and the deposition of a film on a second set of semiconductor product wafers. In some embodiments, a boat with filler wafers is in the reaction chamber when the reaction chamber is heated to the curing temperature. In some examples, the films are deposited by a low pressure chemical vapor deposition (LPCVD) process. With some processes, if the deposition of a film on product wafers is at a temperature below a certain temperature, the film deposited with the product wafer on a boat, filler wafers, and/or other structures in the reaction chamber can cause contamination of product wafers subsequently deposited with a film in the presence of the boat and filler wafers. Contamination from these previously deposited films is inhibited by applying a curing temperature to the deposited fillers in the absence of the product wafers before a film is deposited on the next set of product wafers.